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參數(shù)資料
| 型號(hào)： | AD7878JPZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/DSP INT 28-PLCC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 95.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線(xiàn)） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，雙極 |
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AD7878
–3–
REV. A
Limit at TMIN, TMAX
Parameter
(L Grade)
(J, K, A, B Grades)
(S Grade)
Units
Conditions/Comments
tl
65
75
ns max
CLK IN to
BUSY Low Propagation Delay
t2
65
75
ns max
CLK IN to
BUSY High Propagation Delay
t3
2 CLK IN Cycles
min
CONVST Pulse Width
t4
0
ns min
CS to DMRD/REGISTER ENABLE Setup Time
t5
0
ns min
CS to DMRD/ REGISTER ENABLE Hold Time
t6
45
60
ns min
DMRD Pulse Width
50
s max
t7
16
ns min
ADD0 to
DMRD/REGISTER ENABLE Setup Time
t8
0
ns min
ADD0 to
DMRD/REGISTER ENABLE Hold Time
t9
2
41
57
ns min
Data Access Time after
DMRD
t10
3
5
ns min
Bus Relinquish Time
45
ns max
t11
42
55
ns min
REGISTER ENABLE Pulse Width
50
s max
t12
20
30
ns min
Data Valid to REGISTER ENABLE Setup Time
t13
10
ns min
Data Hold Time after REGISTER ENABLE
t14
2
41
57
ns min
Data Access Time after BUSY
tRESET
2 CLK IN Cycles
min
RESET Pulse Width
NOTES
1Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25
°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t
9 and t14 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
10 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
(VDD = 5 V
5%, VCC = 5 V
5%, VSS = –5 V
5%)
TIMING CHARACTERISTICS1
Figure 1. Load Circuits for Access Time
Figure 2. Load Circuits for Output Float Delay
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
VDD to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
Digital Inputs to DGND
CLK IN,
DMWR, DMRD, RESET,
CS, CONVST, ADD0 . . . . . . . . . . . . –0.3 V to V
DD +0.3 V
Digital Outputs to DGND
ALFL, BUSY . . . . . . . . . . . . . . . . . . –0.3 V to V
DD +0.3 V
Data Pins
DB11–DB0 . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0
°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25
°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55
°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . 1000 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
a. High-Z to VOH
b. High-Z to VOL
a. VOH to High-Z
b. VOL to High-Z
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參數(shù)描述 |
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| AD7878JPZ-REEL | 功能描述:IC ADC 12BIT W/DSP 28PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
| AD7878KN | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Parallel 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:COMPLETE 12 BIT ADC IC - Bulk |
| AD7878KP | 制造商:Rochester Electronics LLC 功能描述:12-BIT ADC IC - Bulk 制造商:Analog Devices 功能描述: |
| AD7878KPZ | 功能描述:IC ADC 12BIT W/DSP INT 28-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:- |
| AD7878KPZ-REEL | 功能描述:IC ADC 12BIT W/DSP 28PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
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