VDD = +5 V ± 5%, V
參數(shù)資料
型號(hào)： AD7875LPZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SAMPLING 5V 28-PLCC
產(chǎn)品變化通告： Conversion Time Change
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 95mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7870/AD7875/AD7876
Rev. C | Page 6 of
28
TIMING CHARACTERISTICS
VDD = +5 V ± 5%, VSS = 5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are
sample tested at 25°C to ensure compliance, unless otherwise noted. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V)
and timed from a voltage level of 1.6 V.
Table 3.
Parameter1
Limit at TMIN, TMAX
(J, K, L, A, B, C Versions)
Limit at TMIN, TMAX
(T Version)
Units
Conditions/Comments
t1
50
ns min
CONVST pulse width
t2
0
ns min
CS to RD setup time (Mode 1)
t32
60
75
ns min
RD pulse width
t4
0
ns min
CS to RD hold time (Mode 1)
t5
70
ns max
RD to INT delay
57
70
ns max
Data access time after RD
5
ns min
Bus relinquish time after RD
50
ns max
t8
0
ns min
HBEN to RD setup time
t9
0
ns min
HBEN to RD hold time
t10
100
ns min
SSTRB to SCLK falling edge setup time
t115
370
ns min
SCLK cycle time
t126
135
150
ns max
SCLK to valid data delay. CL = 35 pF
t13
20
ns min
SCLK rising edge to SSTRB
100
ns max
t14
10
ns min
Bus relinquish time after SCLK
100
ns max
t15
60
ns min
CS to RD setup time (Mode 2)
t16
120
ns max
CS to BUSY propagation delay
t17
200
ns min
Data setup time prior to BUSY
t18
0
ns min
CS to RD hold time (Mode 2)
t19
0
ns min
HBEN to CS setup time
t20
0
ns min
HBEN to CS hold time
1 Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.
2 Timing specifications for t3, t6, and for the maximum limit at t7 are 100% production tested.
3 t6 is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4 t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5.
5 SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6 SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩ||CL) and thus the time to reach 2.4 V.
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參數(shù)描述
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