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| 型號： | AD7869JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete, 14-Bit Analog I/O System |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 297K |
| 代理商： | AD7869JR |
REV. A
–2–
AD7869–SPECIFICATIONS
ADC SECTION
All specifications T
MN
to T
MAX
unless otherwse noted.)
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V, f
CLK
= 2.0 MHz external.
Parameter
J Version
1
A Version
1
Units
T est Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
3, 4
(SNR) @ +25
°
C
T
to T
T otal Harmonic Distortion (T HD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
T rack/Hold Acquisition T ime
78
78
–86
–86
78
77
–86
–86
dB min
dB min
dB typ
dB typ
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
–86
–88
2
–86
–88
2
dB typ
dB typ
μ
s max
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
DC ACCURACY
Resolution
Minimum Resolution
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error
5
Negative Gain Error
5
14
14
±
2
±
1
±
20
±
20
±
20
14
14
±
2
±
1
±
20
±
20
±
20
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
No Missing Codes Are Guaranteed
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUT PUT
6
RO ADC @ +25
°
C
RO ADC T C
±
3
±
1
±
3
±
1
Volts
mA max
2.99/3.01
±
25
2.99/3.01
±
25
±
40
V min/ V max
ppm/
°
C typ
±
ppm/
°
C max
Reference Load Sensitivity
(
RO ADC vs.
I)
–1.5
–1.5
mV max
Reference Load Current Change (0–500
μ
A),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUT S
(
CONVST
, CLK , CONT ROL)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
Input Current
(CONT ROL & CLK )
Input Capacitance, C
IN8
LOGIC OUT PUT S
DR,
RFS
Outputs
Output Low Voltage, V
OL
RCLK Output
Output Low Voltage, V
OL
DR,
RFS
, RCLK Outputs
Floating-State Leakage Current
Floating-State Output Capacitance
8
2.4
0.8
±
10
±
10
10
2.4
0.8
±
10
±
10
10
V min
V max
μ
A max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
V
IN
= V
SS
to DGND
0.4
0.4
V max
I
SINK
= 1.6 mA, Pull-Up Resistor = 4.7 k
0.4
0.4
V max
I
SINK
= 2.6 mA, Pull-Up Resistor = 2 k
±
10
15
±
10
15
μ
A max
pF max
CONVERSION T IME
External Clock
Internal Clock
10
10
10
10
μ
s max
μ
s max
T he Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENT S
V
DD
V
SS
I
DD
I
SS
T otal Power Dissipation
For Both DAC and ADC
±
5% for Specified Performance
±
5% for Specified Performance
Cumulative Current from the T wo V
DD
Pins
Cumulative Current from the T wo V
SS
Pins
T ypically 130 mW
+5
–5
22
12
170
+5
–5
22
12
170
V nom
V nom
mA max
mA max
mW max
NOT ES
1
T emperature ranges are as follows: J Version, 0
°
C to +70
°
C; A Version, –40
°
C to +85
°
C.
2
V
=
±
3 V.
3
SNR calculation includes distortion and noise components.
4
SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5
Measured with respect to internal reference.
6
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7
T ying the CONT ROL input to V
places the device in a factory test mode where normal operation is not exhibited.
8
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
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