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參數(shù)資料
| 型號： | AD7869AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete, 14-Bit Analog I/O System |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 297K |
| 代理商： | AD7869AQ |
AD7869
–5–
REV. A
AD7869 PIN FUNCT ION DE SCRIPT ION
DIP Pin
Number
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 & 17
Mnemonic
Function
V
DD
V
SS
AGND
DGND
Positive Power Supply, 5 V
±
5%. Both V
DD
pins must be tied together.
Negative Power Supply, –5 V
±
5%. Both V
SS
pins must be tied together.
Analog Ground. Both AGND pins must be tied together.
Digital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCE
21
V
IN
9
V
OUT
ADC Analog Input. T he ADC input range is
±
3 V.
Analog Output Voltage from DAC. T his output comes from a buffer amplifier. T he range is bipolar,
±
3 V
with RI DAC = +3 V.
Voltage Reference Output. T he internal ADC 3 V reference is provided at this pin. T his output may be used as a
reference for the DAC by connecting it to the RI DAC input. T he external load capability of this reference is 500
μ
A.
DAC Voltage Reference Output. T his is one of two internal voltage references. T o operate the DAC with this
internal reference, RO DAC should be connected to RI DAC. T he external load capability of the reference is 500
μ
A.
DAC Voltage Reference Input. T he voltage reference for the DAC must be applied to this pin. It is internally
buffered before being applied to the DAC. T he nominal reference voltage for correct operation of the AD7869 is 3 V.
20
RO ADC
11
RO DAC
12
RI DAC
ADC INT ERFACE AND CONT ROL
2
CLK
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying this pin to V
SS
enables the internal laser-trimmed oscillator.
Receive Frame Synchronization, Logic Output. T his is an active low open-drain output that provides a framing
pulse for serial data. An external 4.7 k
pull-up resistor is required on
RFS
.
Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external
ADC clock. If the CONT ROL input is at V
SS
, the clock runs continuously. With the CONT ROL input at DGND,
the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 k
pull-up resistor.
Receive Data, Logic Output. T his is an open-drain data output used in conjunction with
RFS
and RCLK to transmit
data from the ADC. Serial data is valid on the falling edge of RCLK when
RFS
is low. An external 4.7 k
resistor is
required on the DR output.
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold
mode and starts an ADC conversion. T his input is asynchronous to the CLK input.
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-
uous. Note, tying this pin to V
DD
places the part in a factory test mode where normal operation is not exhibited.
DAC INT ERFACE AND CONT ROL
14
TFS
T ransmit Frame Synchronization, Logic Input. T his is a frame or synchronization signal for the DAC with serial
data expected after the falling edge of this signal.
15
DT
T ransmit Data, Logic Input. T his is the data input that is used in conjunction with
TFS
and T CLK to transfer
serial data to the input latch.
16
T CLK
T ransmit Clock, Logic Input. Serial data bits are latched on the falling edge of T CLK when
TFS
is low.
13
LDAC
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
of this signal.
18
NC
No Connect.
3
RFS
4
RCLK
5
DR
1
CONVST
24
CONT ROL
SOIC
0.01 (0.254)
0.006 (0.15)
0.019 (0.49)
0.014 (0.35)
0.096 (2.44)
0.089 (2.26)
0.05
(1.27)
BSC
0.013 (0.32)
0.009 (0.23)
0.042 (1.067)
0.018 (0.457)
6
°
0
°
0.03 (0.76)
0.02 (0.51)
x 45
°
0.708 (18.02)
0.696 (17.67)
0.414 (10.52)
0.398 (10.10)
0.299 (7.6)
0.291 (7.39)
28
15
14
1
1. LEAD NO. 1 INDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
DIP
V
DD
V
SS
RO ADC
DGND
TCLK
DT
RI DAC
AGND
CONTROL
CLK
RCLK
DR
DGND
AGND
RO DAC
NC
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
24
23
22
21
20
19
18
17
16
15
14
12
13
AD7869
TOP VIEW
(Not to Scale)
CONVST
RFS
V
OUT
V
IN
TFS
LDAC
V
DD
V
SS
PIN CONFIGURAT IONS
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| AD7869JN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, 14-Bit Analog I/O System |
| AD7869JNZ | 功能描述:IC I/O PORT 14BIT ANLG 24DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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| AD7869JR | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Single DAC 14-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:DATA ACQ SYS SGL ADC SGL DAC 14BIT 28SOIC W - Rail/Tube |
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