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參數(shù)資料
| 型號(hào)： | AD7868BNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O PORT 12BIT ANLG 24-DIP |
| 產(chǎn)品變化通告： | AD7868 Discontinuation 05/Sept/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 模擬 I/O |
| 接口： | TTL/CMOS |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 通孔 |
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AD7868
–10–
REV. B
AD7868
DAC
LOW-PASS
FILTER
16-BIT
DIGITIZER
MICRO-
CONTROLLER
Figure 11. AD7868 DAC Dynamic Performance Test Circuit
The digitizer sampling is synchronized with the DAC update
rate to ease FFT calculations. The digitizer samples the DAC
output after the output has settled to its new value. Therefore, if
the digitizer were to sample the output directly it would effec-
tively be sampling a dc value each time. As a result, the dynamic
performance of the DAC would not be measured correctly. Us-
ing the digitizer directly on the DAC output would give better
results than the actual performance of the DAC. Using a filter
between the DAC and the digitizer means that the digitizer
samples a continuously moving signal and the true dynamic per-
formance of the AD7868 DAC output is measured.
Figure 12 shows a typical 2048 point Fast Fourier Transform
plot for the AD7868 DAC with an update rate of 83 kHz and an
output frequency of 1 kHz. The SNR obtained from the graph is
73 dBs.
Figure 12. AD7868 DAC FFT Plot
Some applications will require improved performance versus fre-
quency from the AD7868 DAC. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 13 will
extend the very good performance of the DAC to 20 kHz. Other
applications will already have an inherent sample-and-hold
function following the AD7868 DAC output. An example of
this type of application is driving a switched-capacitor filter
where the updating of the DAC is synchronized with the
switched-capacitor filter. This inherent sample-and-hold
function also extends the frequency range performance.
Performance versus Frequency
The typical performance plots of Figures 14 and 15 show the
AD7868’s DAC performance over a wide range of input fre-
quencies at an update rate of 83 kHz. The plot of Figure 14 is
without a sample-and-hold on the DAC output while the plot of
Figure 15 is generated with a sample-and-hold on the output.
AD7868*
LDAC
VOUT
Q
ADG201HS
S1
D1
IN1
AD711
*ADDITIONAL PINS OMITTED FOR CLARITY
R2
2k2
C9
330pF
1s
ONE
SHOT
DELAY
R1
2k2
LDAC
Figure 13. DAC Sample-and-Hold Circuit
TA = +25°C
FREQUENCY – kHz
80
70
0
05
1
SNR
–
dBs
234
40
30
20
10
60
50
Figure 14. DAC Performance vs. Frequency (No Sample-
and-Hold)
TA = +25°C
FREQUENCY – kHz
80
70
0
20
5
SNR
–
dBs
10
15
40
30
20
10
60
50
Figure 15. DAC Performance vs. Frequency (Sample-and-
Hold)
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| AD7868BR | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Single DAC 12-Bit 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:ANALOG I/O PORT IC - Bulk |
| AD7868BR-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2 |
| AD7868BRZ | 功能描述:IC I/O PORT 12BIT ANLG 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2 |
| AD7868BRZ-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2 |
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