參數(shù)資料
型號(hào)： AD7863AR-3
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： RECTIFIER SCHOTTKY DUAL 40A 40V 375A-ifsm 0.58V-vf 1mA-ir TO-3P 30/TUBE
中文描述： 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝： MS-013AE, SOIC-28
文件頁數(shù)： 4/18頁
文件大小： 207K
代理商： AD7863AR-3
AD7863
–4–
REV. A
TIMING CHARACTERISTICS
1, 2
A, B
Versions
Parameter
Units
Test Conditions/Comments
t
CONV
t
ACQ
Parallel Interface
t
1
t
2
t
3
t
4
t
53
t
64
5.2
0.5
μ
s max
μ
s max
Conversion Time
Acquisition Time
0
0
35
45
30
5
30
10
400
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
CS
to
RD
Setup Time
CS
to
RD
Hold Time
CONVST
Pulsewidth
Read Pulsewidth
Data Access Time after Falling Edge of
RD
Bus Relinquish Time after Rising Edge of
RD
t
7
t
8
Time Between Consecutive Reads
Quiet Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figure 1.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= +5 V 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
unless
otherwise noted.)
t
3
t
1
t
4
t
5
t
2
t
6
V
A1
V
A2
V
B1
V
B2
CONVST
BUSY
A0
CS
RD
DATA
t
7
t
CONV
= 5.2 s
t
ACQ
t
8
Figure 1. Timing Diagram
TO OUTPUT
PIN
1.6mA
200 A
50pF
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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