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| 型號(hào)： | AD7859LASZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CHAN LP 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極 |
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AD7859/AD7859L
REV. A
–15–
DC/AC Applications
For dc applications, high source impedances are acceptable,
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. For example with RIN = 5 k
,
the required acquisition time is 922 ns.
For ac applications, removing high frequency components
greater than the Nyquist frequency from the analog input signal
is recommended by use of a low- pass filter on the AIN(+) pin,
as shown in Figure 11. In applications where harmonic distor-
tion and signal to noise ratio are critical, the analog input should
be driven from a low impedance source. Large source imped-
ances significantly affect the ac performance of the ADC. They
may require the use of an input buffer amplifier. The choice of
the amplifier is a function of the particular application.
The maximum source impedance depends on the amount of to-
tal harmonic distortion (THD) that can be tolerated. The THD
increases as the source impedance increases. Figure 10 shows a
graph of the Total Harmonic Distortion vs. analog input signal
frequency for different source impedances. With the setup as in
Figure 11, the THD is at the –90 dB level. With a source im-
pedance of 1 k
and no capacitor on the AIN(+) pin, the THD
increases with frequency.
THD
–
dB
INPUT FREQUENCY – kHz
–72
–76
–92
0
100
20
40
60
80
–88
–80
–84
THD VS. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
RIN = 1k
RIN = 50k, 10nF
AS IN FIGURE 13
Figure 10. THD vs. Analog Input Frequency
In a single supply application (both 3 V and 5 V), the V+ and
V– of the op amp can be taken directly from the supplies to the
AD7859/AD7859L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and out-
puts at frequencies greater than 10 kHz, care must be taken in
selecting the particular op amp for the application. In particular,
for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum per-
formance. Figure 11 shows the arrangement for a single supply
application with a 50
and 10 nF low-pass filter (cutoff fre-
quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
AD820-3V.
ANALOG INPUT
The equivalent analog input circuit is shown in Figure 9. AIN(+)
is the channel connected to the positive input of the track/hold
circuitry and AIN(–) is the channel connected to the negative
input. Please refer to Table IIIa and Table IIIb for channel
configuration.
During the acquisition interval the switches are both in the track
position and the AIN(+) charges the 20 pF capacitor through
the 125
resistance. The rising edge of CONVST switches
SW1 and SW2 go into the hold position retaining charge on the
20 pF capacitor as a sample of the signal on AIN(+). The AIN(–)
is connected to the 20 pF capacitor, and this unbalances the
voltage at node A at the input of the comparator. The capacitor
DAC adjusts during the remainder of the conversion cycle to
restore the voltage at node A to the correct value. This action
transfers a charge, representing the analog input signal, to the
capacitor DAC which in turn forms a digital representation of
the analog input signal. The voltage on the AIN(–) pin directly
influences the charge transferred to the capacitor DAC at the
hold instant. If this voltage changes during the conversion
period, the DAC representation of the analog input voltage is
altered. Therefore it is most important that the voltage on the
AIN(–) pin remains constant during the conversion period.
Furthermore, it is recommended that the AIN(–) pin is always
connected to AGND or to a fixed dc voltage.
CAPACITOR
DAC
COMPARATOR
HOLD
TRACK
SW2
NODE A
20pF
SW1
TRACK
HOLD
125
125
AIN(+)
AIN(–)
AGND
Figure 9. Analog Input Equivalent Circuit
Acquisition Time
The track-and-hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the
track-and-hold amplifier to acquire an input signal will depend
on how quickly the 20 pF input capacitance is charged. There is
a minimum acquisition time of 400 ns. This includes the time
required to change channels. For large source impedances, >2 k
,
the acquisition time is calculated using the formula:
tACQ = 9
× (R
IN + 125
) × 20 pF
where RIN is the source impedance of the input signal, and
125
, 20 pF is the input R, C.
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