參數(shù)資料
型號(hào)： AD7859APZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/28頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 8CH 200KSPS 44PLCC
標(biāo)準(zhǔn)包裝： 27
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 30mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
AD7859/AD7859L
REV. A
–11–
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
START
Figure 4. Flowchart for Reading the Status Register
MSB
ZERO
SGL/DIFF
CHSLT2
CHSLT1
CHSLT0
PMGT1
PMGT0
ONE
AMODE
BUSY
CALMD
CALSLT1
CALSLT0
STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit
Mnemonic
Comment
15
ZERO
These two bits are always 0.
14
ZERO
13
SGL/DIFF
Single/Differential Bit.
12
CHSLT2
Channel Selection Bits. These bits, in conjunction with the SGL/DIFF bit, determine which channel has
11
CHSLT1
been selected for conversion. Please refer to Table IIIa and Table IIIb.
10
CHSLT0
9
PMGT1
Power Management Bits. These bits along with the SLEEP pin indicate if the part is in a power-down
8
PMGT0
mode or not. See Table VI in Power-Down Section for description.
7
ONE
Both these bits are always 1.
6
ONE
5
AMODE
Analog Mode Bit. This bit is used along with SGL/DIFF and CHSLT2 – CHSLT0 to determine the
AIN(+) and AIN(–) inputs to the track and hold circuitry and the analog conversion mode (unipolar or bi-
polar). Please see Table III for details.
4
BUSY
Conversion/Calibration BUSY Bit. When this bit is a 1, there is a conversion or a calibration in progress.
When this bit is a zero, there is no conversion or calibration in progress.
3
CALMD
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see Table IV).
2
CALSLT1
Calibration Selection Bits. The CALSLT1 and CALSLT0 bits indicate which of the calibration
1
CALSLT0
registers are addressed for reading and writing (see section on the Calibration Registers for more details).
0
STCAL
Start Calibration Bit. The STCAL bit is a 1 if a calibration is in progress and a 0 if there is no calibration in
progress.
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