參數(shù)資料
型號(hào)： AD7859APZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CHAN LP 44PLCC
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 30mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
AD7859/AD7859L
REV. A
–22–
Self-Calibration Timing
Figure 29 shows the timing for a software full self-calibration.
Here the BUSY line stays high for the full length of the self-
calibration. A self-calibration is initiated by writing to the
control register and setting the STCAL bit to 1. The BUSY line
goes high at the end of the write to the control register, and
BUSY goes low when the full self-calibration is complete after a
time tCAL as show in Figure 29.
t19
DATA LATCHED INTO
CONTROL REGISTER
HI-Z
DATA
VALID
CS
WR
DATA
BUSY
tCAL
Figure 29. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line is triggered high at the end of the write to the
control register and stays high for the full duration of the self-
calibration. The length of time for which BUSY is high depends
on the type of self-calibration that is initiated. Typical values are
given in Table IX. The timing diagram for the other self-calibration
options is similar to that outlined in Figure 29.
System Calibration Description
System calibration allows the user to remove system errors ex-
ternal to the AD7859/AD7859L, as well as remove the errors of
the AD7859/AD7859L itself. The maximum calibration range
for the system offset errors is
±5% of V
REF and for the system
gain errors, it is
±2.5% of V
REF. If the system offset or system
gain errors are outside these ranges, the system calibration algo-
rithm reduces the errors as much as the trim range allows.
Figures 30 through 32 illustrate why a specific type of system
calibration might be used. Figure 30 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be removed by a system offset calibration.
MAX SYSTEM FULL SCALE
IS
±2.5% FROM V
REF
MAX SYSTEM OFFSET
IS
±5% OF V
REF
ANALOG
INPUT
RANGE
VREF + SYS OFFSET
VREF – 1LSB
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
AGND
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS
±5% OF V
REF
Figure 30. System Offset Calibration
Figure 31 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
ANALOG
INPUT
RANGE
MAX SYSTEM FULL SCALE
IS
±2.5% FROM V
REF
SYSTEM GAIN
CALIBRATION
ANALOG
INPUT
RANGE
VREF – 1LSB
AGND
SYS FULL S.
MAX SYSTEM FULL SCALE
IS
±2.5% FROM V
REF
VREF – 1LSB
SYS FULL S.
AGND
Figure 31. System Gain Calibration
Finally in Figure 32 both the system offset error and gain error
are removed by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is adjusted at
the top end to account for the system full scale.
MAX SYSTEM FULL SCALE
IS
±2.5% FROM V
REF
ANALOG
INPUT
RANGE
VREF + SYS OFFSET
SYS OFFSET
AGND
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS
±5% OF V
REF
MAX SYSTEM OFFSET
IS
±5% OF V
REF
SYSTEM GAIN
CALIBRATION
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
VREF – 1LSB
SYS F.S.
MAX SYSTEM FULL SCALE
IS
±2.5% FROM V
REF
Figure 32. System (Gain + Offset) Calibration
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