AVDD,
參數(shù)資料
型號(hào)： AD7856ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/32頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 8CHAN 5V 24SOIC
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 14
采樣率（每秒）： 285k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)偽差分，單極
–3–
REV. A
AD7856
Parameter
A Version
1
K Version
1
Units
Test Conditions/Comments
POWER PERFORMANCE
AVDD, DVDD
+4.75/+5.25
V min/max
IDD
Normal Mode
5
17
mA max
AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA
Sleep Mode
6
With External Clock On
30
10
A typ
Full Power-Down. Power Management Bits in Con-
trol Register Set as PMGT1 = 1, PMGT0 = 0
400
500
A typ
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off
5
A max
Typically 0.5
A. Full Power-Down. Power Manage-
ment. Bits in Control Register Set as PMGT1 = 1,
PMGT0 = 0
200
A typ
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation
89.25
mW max
VDD = 5.25 V. Typically 60 mW; SLEEP = VDD
Sleep Mode Power Dissipation
With External Clock On
52.5
W typ
VDD = 5.25 V. SLEEP = 0 V
With External Clock Off
26.25
W max
VDD = 5.25 V. Typically 5.25 W; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.0375
× V
REF/–0.0375 × VREF
V max/min
Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.01875
× V
REF/–0.98125 × VREF
V max/min
Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A Version: –40
°C to +105°C. K Version: 0°C to +105°C.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25
°C to ensure compliance.
5All digital inputs @ DGND except for
CONVST, SLEEP, CAL and SYNC @ DV
DD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL, and SYNC @ DV
DD. No load on the digital outputs.
Analog inputs @ AGND.
7The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±0.0375 × V
REF, and
the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V REF ± 0.01875 × VREF).
This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
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