AVDD,
參數(shù)資料
型號(hào)： AD7851ARZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/36頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 333KSPS 24-SOIC
標(biāo)準(zhǔn)包裝： 31
位數(shù)： 14
采樣率（每秒）： 333k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極
AD7851
–4–
REV. B
Parameter
Version A
1
Version K
1
Unit
Test Conditions/Comments
POWER PERFORMANCE
AVDD, DVDD
4.75/5.25
V min/max
IDD
Normal Mode
4
17
mA max
AVDD = DVDD = 4.75 V to 5.25 V. Typically
12 mA.
Sleep Mode
5
With External Clock On
20
A typ
Full Power-Down. Power management bits
in control register set as PMGT1 = 1, PMGT0 = 0.
600
A typ
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
With External Clock Off
10
A max
Typically 1
A. Full Power-Down. Power
management bits in control register set as
PMGT1 = 1, PMGT0 = 0.
300
A typ
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Normal Mode Power Dissipation
89.25
mW max
VDD = 5.25 V: Typically 63 mW; SLEEP = VDD.
Sleep Mode Power Dissipation
With External Clock On
105
W typ
VDD = 5.25 V; SLEEP = 0 V.
With External Clock Off
52.5
W max
VDD = 5.25 V; Typically 5.25
W; SLEEP = 0 V.
SYSTEM CALIBRATION
Offset Calibration Span
6
+0.05
× V
REF/–0.05
× V
REF
V max/min
Allowable Offset Voltage Span for Calibration.
Gain Calibration Span
6
+1.025
× V
REF/–0.975
× V
REF
V max/min
Allowable Full-Scale Voltage Span for Calibration.
NOTES
1Temperature ranges as follows: A Version, –40
°C to +125°C; K Version, 0°C to 125°C.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4All digital inputs at DGND except for
CONVST, SLEEP, CAL, and SYNC at DV
DD. No load on the digital outputs. Analog inputs at AGND.
5CLKIN at DGND when external clock off. All digital inputs at DGND except for
CONVST, SLEEP, CAL, and SYNC at DV
DD. No load on the digital outputs.
Analog inputs at AGND.
6The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
± 0.05 × V
REF, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF
± 0.025 × V
REF). This is
explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
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