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參數資料
| 型號： | AD7843ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT TOUCHSCREEN 16TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評估套件： | 可供 |
| 數據接口： | 串行 |
| 數據速率/采樣率 (SPS，BPS)： | 125k |
| 電壓基準： | 外部 |
| 電源電壓： | 2.2 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD7843EBZ-ND - BOARD EVAL FOR AD7843 |
AD7843
Rev. B | Page 17 of 20
DETAILED SERIAL INTERFACE TIMING
Figure 25 shows the detailed timing diagram for serial
interfacing to the AD7843. Writing information to the control
register takes place on the first eight rising edges of DCLK in a
data transfer. The control register is written to only if a START
bit is detected (see the Control Register section) on DIN. The
initiation of the following conversion also depends on the
presence of the START bit. Throughout the eight DCLK cycles
when data is being written to the part, the DOUT line is driven
low. The MSB of the conversion result is clocked out on the
falling edge of the ninth DCLK cycle and is valid on the rising
edge of the tenth DCLK cycle; therefore, nine leading zeros can
be clocked out prior to the MSB. This means the data seen on
the DOUT line in the 24 DCLK conversion cycle is presented in
the form of nine leading zeros, twelve bits of data, and three
trailing zeros.
The rising edge of CS puts the bus and the BUSY output back
into three-state, the DIN line is ignored, and, if a conversion is
in progress at the time, this is also aborted. However, if CS is not
brought high after the completion of the conversion cycle, then
the part waits for the next START bit to initiate the next
conversion. This means that each conversion does not
necessarily need to be framed by CS, because once CS goes low,
the part detects each START bit and clocks in the control word
after it on DIN. When the AD7843 is in the 12-bit conversion
mode, a second START bit is not detected until seven DCLK
pulses have elapsed after a control word is clocked in on DIN,
that is, another START bit can be clocked in on the eighth
DCLK rising edge after a control word is written to the device
(see the Fifteen Clocks per Cycle section). If the device is in the
8-bit conversion mode, a second START bit is not recognized
until three DCLK pulses elapse after the control word is clocked
in, that is, another START bit can be clocked in on the fourth
DCLK rising edge after a control word is written to the device.
Because a START bit can be recognized during a conversion, the
control word for the next conversion can be clocked in during
the current conversion, enabling the AD7843 to complete a
conversion cycle in less than 24 DCLKs.
02144-B
-025
CS
DCLK
DIN
BUSY
DOUT
DB11
PD0
DB10
t1
t4
t5
t6
t9
t10
t11
t7
t2
t3
t8
t12
Figure 25. Detailed Timing Diagram
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