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參數(shù)資料
| 型號(hào)： | AD7837BR |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 250k |
AD7837/AD7847
REV. C
–8–
VALID
DATA
t6
t3
t8
WR
DATA
ADDRESS DATA
t7
t1
t2
t5
t4
CS
A0/A1
LDAC
Figure 14. AD7837 Write Cycle Timing Diagram
CS, WR, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided that
LDAC is held high, there is no analog output change as a result
of loading data to the input latches. Address lines A0 and A1
determine which latch data is loaded to when
CS and WR are low.
The control logic truth table for the part is shown in Table II.
Table II. AD7837 Truth Table
CS WR A1 A0 LDAC Function
1
X
1
No Data Transfer
X
1
X
1
No Data Transfer
0
1
DAC A LS Input Latch Transparent
0
1
DAC A MS Input Latch Transparent
0
1
0
1
DAC B LS Input Latch Transparent
0
1
DAC B MS Input Latch Transparent
1
X
0
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
X = Don’t Care.
The
LDAC input controls the transfer of 12-bit data from the
input latches to the DAC latches. When
LDAC is taken low, both
DAC latches, and hence both analog outputs, are updated at
the same time. The data in the DAC latches is held on the rising
edge of
LDAC. The LDAC input is asynchronous and indepen-
dent of
WR. This is useful in many applications especially in the
simultaneous updating of multiple AD7837s. However, care must
be taken while exercising
LDAC during a write cycle. If an LDAC
operation overlaps a
CS and WR operation, there is a possibility
of invalid data being latched to the output. To avoid this,
LDAC
must remain low after
CS or WR return high for a period equal
to or greater than t8, the minimum LDAC pulsewidth.
UNIPOLAR BINARY OPERATION
Figure 15 shows DAC A on the AD7837/AD7847 connected
for unipolar binary operation. Similar connections apply for
DAC B. When VIN is an ac signal, the circuit performs 2-quad-
rant multiplication. The code table for this circuit is shown in
Table III. Note that on the AD7847 the feedback resistor RFB is
internally connected to VOUT.
DAC A
AGNDA
VOUTA
VREFA
VIN
DGND
VSS
RFBA
*
VSS
VDD
AD7837
AD7847
VOUT
*INTERNALLY
CONNECTED
ON AD7847
Figure 15. Unipolar Binary Operation
Table III. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output, VOUT
1111 1111 1111
–VIN
×
4095
4096
1000 0000 0000
–VIN
×
2048
4096
= –1/ 2 V
IN
0000 0000 0001
–VIN
×
1
4096
0000 0000 0000
0 V
Note 1 LSB =
V
IN
4096
.
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