t2 t
參數(shù)資料
型號(hào)： AD7829BRUZ-1
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 0K
描述： IC ADC 8BIT 8CH 2MSPS 28-TSSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 8
采樣率（每秒）： 2M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 36mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極
AD7829-1
Rev. 0 | Page 13 of 20
CONVST
DB0 TO DB7
A0 TO A2
EOC
CS
RD
t2
t1
t3
t13
VALID
DATA
ADDRESS CHANNEL y
TRACK CHx
HOLD CHx
TRACK CHy
HOLD CHy
120ns
0
61
79-
015
Capacitor C2 in Figure 13 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track-
and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, while Switch 2 is that of
the sampling capacitor, as shown in Figure 4 and Figure 5.
VIN
C2
4pF
D1
D2
R1
310
SW1
C1
0.5pF A
B
SW2
VDD
0
61
79
-01
4
Figure 14. Channel Hopping Timing
Figure 13. Equivalent Analog Input Circuit
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t13. This is the
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance.
When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens, while Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the
Figure 15 shows the typical
performance of the AD7829-1 when channel hopping for
various acquisition times. These results were obtained using an
external reference and internal VMID while channel hopping
between VIN1 and VIN4 with 0 V on Channel 4 and 0.5 V on
Channel 1.
Circuit Description section), after
which it returns to track mode and the ADC enters its
conversion phase. At this point, Switch 1 opens and Switch 2
moves to Position B. At the end of the conversion, Switch 2
moves back to Position A.
ACQUISITION TIME (ns)
8.0
5.0
10
500
200
EN
O
B
100
50
40
30
20
15
7.5
7.0
6.5
6.0
5.5
8.5
06
17
9-
0
16
Analog Input Selection
On power-up, the default VIN selection is VIN1. When returning
to normal operation from power-down, the VIN selected is the
same one that was selected prior to power-down being initiated.
Table 6 shows the multiplexer address corresponding to each
analog input from VIN1 to VIN8 for the AD7829-1.
Table 6.
A2
A1
A0
Analog Input Selected
0
VIN1
0
1
VIN2
0
1
0
VIN3
0
1
VIN4
1
0
VIN5
Figure 15. Effective Number of Bits vs. Acquisition Time for the AD7829-1
1
0
1
VIN6
1
0
VIN7
The on-chip track-and-hold can accommodate input
frequencies to 10 MHz, making the AD7829-1 ideal for
subsampling applications. When the AD7829-1 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dB, as shown in
1
VIN8
Channel selection on the AD7829-1 is made without the
necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read
operation, that is, on the falling edge of
RD
CS
while
is low, as
shown in Figure 14. This allows for improved throughput rates
in “channel hopping” applications.
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