VDD PD CONVST tPOWE" />
  • 參數(shù)資料
    型號(hào): AD7829BRU
    廠商: Analog Devices Inc
    文件頁數(shù): 7/28頁
    文件大?。?/td> 0K
    描述: IC ADC 8BIT 8CH 2MSPS 28TSSOP
    標(biāo)準(zhǔn)包裝: 50
    位數(shù): 8
    采樣率(每秒): 2M
    數(shù)據(jù)接口: 并聯(lián)
    轉(zhuǎn)換器數(shù)目: 1
    功率耗散(最大): 36mW
    電壓電源: 單電源
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
    供應(yīng)商設(shè)備封裝: 28-TSSOP
    包裝: 管件
    輸入數(shù)目和類型: 8 個(gè)單端,單極
    AD7822/AD7825/AD7829
    Rev. C | Page 15 of 28
    VDD
    PD
    CONVST
    tPOWER-UP
    1s
    tPOWER-UP
    1s
    CONVERSION
    INITIATED HERE
    CONVERSION
    INITIATED HERE
    EXTERNAL REFERENCE
    CONVERSION
    INITIATED HERE
    CONVERSION
    INITIATED HERE
    VDD
    PD
    CONVST
    tPOWER-UP
    ON-CHIP REFERENCE
    25s
    0
    1321-
    020
    Figure 20. AD7822/AD7825 Power-Up Time
    POWER VS. THROUGHPUT
    Superior power performance can be achieved by using the
    automatic power-down (Mode 2) at the end of a conversion
    (see the Operating Modes section).
    Figure 21 shows how the automatic power-down is implemented
    using the CONVST signal to achieve the optimum power
    performance for the AD7822/AD7825/AD7829. The duration
    of the CONVST pulse is set to be equal to or less than the power-up
    time of the devices (see the Operating Modes section). As the
    throughput rate is reduced, the device remains in its power-
    down state longer and the average power consumption over time
    drops accordingly.
    tPOWER-UP
    1s
    330ns
    tCONVERT
    POWER-DOWN
    tCYCLE
    10s @ 100kSPS
    CONVST
    0
    1321-
    0
    22
    Figure 21. Automatic Power-Down
    For example, if the AD7822 is operated in a continuous
    sampling mode, with a throughput rate of 100 kSPS and using
    an external reference, the power consumption is calculated as
    follows. The power dissipation during normal operation is
    36 mW, VDD = 3 V. If the power-up time is 1 μs and the conversion
    time is 330 ns (@ +25°C), the AD7822 can be said to dissipate
    36 mW (maximum) for 1.33 μs during each conversion cycle.
    If the throughput rate is 100 kSPS, the cycle time is 10 μs and
    the average power dissipated during each cycle is (1.33/10) ×
    (36 mW) = 4.79 mW. This calculation uses the minimum
    conversion time, thus giving the best-case power dissipation at
    this throughput rate. However, the actual power dissipated
    during each conversion cycle could increase, depending on the
    actual conversion time (up to a maximum of 420 ns).
    Figure 22 shows the power vs. throughput rate for automatic
    full power-down.
    THROUGHPUT (kSPS)
    100
    10
    0
    5
    0100
    P
    O
    WE
    R
    (
    m
    W)
    1
    200
    300
    400
    0.1
    50
    150
    250
    350
    450
    01
    32
    1-
    0
    23
    Figure 22. AD7822/AD7825/AD7829 Power vs. Throughput
    FREQUENCY (kHz)
    0
    –10
    –80
    (dB
    )
    –40
    –50
    –60
    –70
    –20
    –30
    0
    113 14
    2
    170 198 22
    7
    255 283 31
    2
    34
    0
    368 396 42
    5
    453 481 51
    0
    53
    8
    566 595 62
    3
    651 680 70
    8
    73
    6
    765 793 82
    1
    850 878 90
    6
    93
    5
    963
    28 57 85
    991
    2048 POINT FFT
    SAMPLING
    2MSPS
    fIN = 200kHz
    0
    132
    1-
    0
    24
    Figure 23. AD7822/AD7825/AD7829 SNR
    OPERATING MODES
    The AD7822/AD7825/AD7829 have two possible modes of
    operation, depending on the state of the CONVST pulse
    approximately 100 ns after the end of a conversion, that is, upon
    the rising edge of the EOC pulse.
    Mode 1 Operation (High Speed Sampling)
    When the AD7822/AD7825/AD7829 are operated in Mode 1,
    they are not powered down between conversions. This mode of
    operation allows high throughput rates to be achieved.
    Figure 24 shows how this optimum throughput rate is achieved
    by bringing CONVST high before the end of a conversion, that
    is, before the EOC pulses low. When operating in this mode, a
    new conversion should not be initiated until 30 ns after the end
    of a read operation. This allows the track-and-hold to acquire
    the analog signal to 0.5 LSB accuracy.
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