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參數(shù)資料
| 型號(hào)： | AD7822 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1-Channel Sampling ADCs(2MSPS,單通道采樣8位A/D轉(zhuǎn)換器) |
| 中文描述： | 單通道采樣ADC（2MSPS，單通道采樣8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 238K |
| 代理商： | AD7822 |
AD7822/AD7825/AD7829
–5–
REV. 0
PIN FUNCT ION DE SCRIPT IONS
Mnemonic
Description
V
IN1
to V
IN8
Analog Input Channels. T he AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. T he inputs have an input span of 2.5 V and 2 V depending on the supply
voltage (V
DD
). T his span may be centered anywhere in the range AGND to V
DD
using the V
MID
Pin. T he
default input range (V
MID
unconnected) is AGND to 2 V (V
DD
= 3 V
±
10%) or AGND to 2.5 V (V
DD
= 5 V
±
10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V
±
10% and 5 V
±
10%.
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input Signal. T he convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. T he falling edge of this signal places the track/hold in hold mode. T he track/hold goes into track
mode again 120 ns after the start of a conversion. T he state of the
CONVST
signal is checked at the end of a
conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Mode section of
the data sheet.)
Logic Output. T he End of Conversion signal indicates when a conversion has finished. T he signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
face section of this data sheet.)
Logic input signal. T he chip select signal is used to enable the parallel port of the AD7822, AD7825 and AD7829.
T his is necessary if the ADC is sharing a common data bus with another device.
Logic Input. T he Power-Down pin is present on the AD7822 and AD7825 only. Bringing the
PD
pin low
places the AD7822 and AD7825 in Power-Down mode. T he ADCs will power-up when
PD
is brought logic
high again.
Logic Input Signal. T he read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. T he signal is internally gated with the
CS
signal. Both
RD
and
CS
must be logic
low to enable the data bus.
Channel Address Inputs. T he address of the next multiplexer channel must be present on these inputs when the
RD
signal goes low.
Data Output Lines. T hey are normally held in a high impedance state. Data is driven onto the data bus when
both
RD
and
CS
go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825 and AD7829 at this
V
DD
AGND
DGND
CONVST
EOC
CS
PD
RD
A0–A2
DB0–DB7
VREF
IN
/REF
OUT
PIN CONFIGURAT IONS
DIP/SOIC/T SSOP
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
(TOP VIEW
AD7822
NC = NO CONNECT
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
AGND
DB7
CS
RD
DGND
EOC
PD
NC
V
IN1
V
MID
V
REF
13
16
15
14
24
23
22
21
20
19
18
17
(TOP VIEW
12
11
10
9
8
1
2
3
4
7
6
5
AD7825
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
V
REF
AGND
DB7
CS
RD
DGND
EOC
A1
A0
V
IN1
V
IN2
V
IN3
V
MID
PD
V
IN4
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
(TOP VIEW
28
27
26
25
24
23
22
21
AD7829
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
V
REF
AGND
DB7
CS
RD
DGND
EOC
A2
A1
V
IN1
V
IN2
V
IN3
V
MID
A0
V
IN8
V
IN7
V
IN6
V
IN5
V
IN4
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