參數(shù)資料
型號: AD7814
廠商: Analog Devices, Inc.
元件分類: 溫度/濕度傳感器
英文描述: 10-Bit Digital Temperature Sensor in 6-Lead SOT-23(10位數(shù)字溫度傳感器)
中文描述: 10位數(shù)字溫度傳感器在6引腳SOT - 23(10位數(shù)字溫度傳感器)
文件頁數(shù): 2/8頁
文件大?。?/td> 89K
代理商: AD7814
REV. 0
–2–
AD7814–SPECIFICATIONS
1, 2
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
±
2.0
±
2.5
±
3.5
°
C
°
C
°
C
Bits
μ
s
μ
s
T
A
= 0
°
C to +85
°
C. V
DD
= +3 V to +5.5 V
3
T
A
= –40
°
C to 0
°
C. V
DD
= +3 V to +5.5 V
3
T
A
= –55
°
C to +125
°
C. V
DD
= +3 V to +5.5 V
±
2.0
10
400
25
Resolution
Update Rate, t
R
Temperature Conversion Time
SUPPLIES
Supply Voltage
Supply Current
Normal Mode
Shutdown Mode
Power Dissipation
Power Dissipation
1 sps
10 sps
100 sps
2.7
5.5
V
For Specified Performance
250
1
80
400
3
μ
A
μ
A
μ
W
V
DD
= +3 V. Using Normal Mode
V
DD
= +3 V. Using Shutdown Mode
3
3.3
6
μ
W
μ
W
μ
W
DIGITAL INPUT
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IN
Input Capacitance, C
IN
2.4
V
V
μ
A
pF
0.8
±
1
10
V
IN
= 0 V to V
DD
All Digital Inputs
DIGITAL OUTPUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Capacitance, C
OUT
V
DD
– 0.3 V
I
SOURCE
= I
SINK
= 200
μ
A
I
OL
= 200
μ
A
0.4
50
V
pF
NOTES
1
All specifications apply for –55
°
C to +125
°
C unless otherwise stated.
2
Guaranteed by design and characterization, not production tested.
3
For V
DD
= +2.7 V to +3 V and T
A
= –40
°
C to +85
°
C, the typical temperature error is
±
2
°
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter
Limit
Units
Comments
t
1
t
2
t
3
t
44
t
5
t
6
t
7
t
84
0
50
50
35
20
0
0
40
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
CS
to SCLK Setup Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time After SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Hold Time After SCLK Rising Edge
CS
to SCLK Hold Time
CS
to DOUT High Impedance
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
3
See Figure 2.
4
Measured with the load circuit of Figure 1.
(T
A
= T
MIN
to T
MAX
, V
DD
= +2.7 V to +5.5 V, unless otherwise noted)
(T
A
= T
MIN
to T
MAX
, V
DD
= +2.7 V to +5.5 V, unless otherwise noted)
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