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參數(shù)資料
| 型號： | AD7812YNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 8CHAN SRL 20DIP |
| 標準包裝： | 18 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | DSP，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極；7 偽差分，單極 |
AD7811/AD7812
–5–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin(s)
AD7811
AD7812
Mnemonic
Description
11
VREF
An external reference input can be applied here. When using an external precision
reference or VDD the EXTREF bit in the control register must be set to logic one. The
external reference input range is 1.2 V to VDD.
22
CREF
Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise
performance of the on-chip reference.
3, 5–7
3, 5–11
VIN1–VIN4(8)
Analog Inputs. The analog input range is 0 V to VREF.
4
AGND
Analog Ground. Ground reference for track/hold, comparator, on-chip reference and
DAC.
8
12
A0
Package Address Pin. This Logic Input can be hardwired high or low. When used in
conjunction with the package address bit in the control register this input allows two
devices to share the same serial bus. For example a twelve channel solution can be
achieved by using the AD7811 and the AD7812 on the same serial bus.
9
13
DGND
Digital Ground. Ground reference for digital circuitry.
10
14
TFS
Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new
control byte should be shifted in on the next 10 falling edges of SCLK.
11
15
RFS
Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in
the serial interface. It is used to provide compatibility with DSPs which use a continuous
serial clock and framing signal. In multipackage applications the RFS Pin can also be
used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a
rising edge on this input. The counter is reset at the end of a serial read operation.
12
16
DOUT
Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial
clock. The output enters a High impedance condition on the rising edge of the 11th
SCLK pulse.
13
17
DIN
Serial Data Input. The control byte is read in at this input. In order to complete a
serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are
shifted in—see Serial Interface section.
14
18
SCLK
Serial Clock Input. An external serial clock is applied to this input to obtain serial data
from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is
clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK.
15
19
CONVST
Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold
Mode on the falling edge of this signal and a conversion is initiated. The state of this
pin at the end of conversion also determines whether the part is powered down or not.
See operating modes section of this data sheet.
16
20
VDD
Positive Supply Voltage 2.7 V to 5.5 V.
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7811
VREF
DIN
SCLK
CONVST
VDD
CREF
VIN1
AGND
TFS
RFS
DOUT
VIN2
VIN3
VIN4
A0
DGND
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7812
VREF
DIN
SCLK
VDD
CREF
VIN1
AGND
TFS
RFS
DOUT
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
A0
DGND
CONVST
C
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