參數(shù)資料
型號(hào)： AD7811YRUZ
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝： TSSOP-16
文件頁(yè)數(shù)： 13/19頁(yè)
文件大?。?/td> 210K
代理商： AD7811YRUZ
–3–
REV. B
AD7811/AD7812
Parameter
Y Version
Unit
Test Conditions/Comments
POWER SUPPLY
VDD
2.7
V min
For Specified Performance
5.5
V max
IDD
Digital Inputs = 0 V or VDD
Normal Operation
3.5
mA max
Power-Down
Full Power-Down
1
A max
Partial Power-Down (Internal Ref)
350
A max
See Power-Up Times Section
Power Dissipation
VDD = 3 V
Normal Operation
10.5
mW max
Auto Full Power-Down
See Power vs. Throughput Section
Throughput 1 kSPS
31.5
W max
Throughput 10 kSPS
315
W max
Throughput 100 kSPS
3.15
mW max
Partial Power-Down (Internal Ref)
1.05
mW max
Full Power-Down
3
W max
NOTES
1See Terminology.
2Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Parameter
Y Version
Unit
Conditions/Comments
t
POWER-UP
1.5
s (max)
Power-Up Time of AD7811/AD7812 after Rising Edge of
CONVST
t
1
2.3
s (max)
Conversion Time
t
2
20
ns (min)
CONVST Pulsewidth
t
3
25
ns (min)
SCLK High Pulsewidth
t
4
25
ns (min)
SCLK Low Pulsewidth
t
5
3
5
ns (min)
RFS Rising Edge to SCLK Rising Edge Setup Time
t
6
3
5
ns (min)
TFS Falling Edge to SCLK Falling Edge Setup Time
t
7
3
10
ns (max)
SCLK Rising Edge to Data Out Valid
t
8
10
ns (min)
DIN Data Valid to SCLK Falling Edge Setup Time
t
9
5
ns (min)
DIN Data Valid after SCLK Falling Edge Hold Time
t
10
3, 4
20
ns (max)
SCLK Rising Edge to DOUT High Impedance
t
11
100
ns (min)
DOUT High Impedance to
CONVST Falling Edge
NOTES
1Sample tested to ensure compliance.
2See Figures 16, 17 and 18.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD = 5 V
± 10% and
0.4 V or 2 V for VDD = 3 V
± 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)
2.1V
200 A
CL
50pF
IOH
TO
OUTPUT
PIN
IOL
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
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