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參數(shù)資料
| 型號： | AD7811YRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 4CHAN SRL 16-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | DSP，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；3 個偽差分，單極 |
AD7811/AD7812
–16–
REV. B
RFS. The first rising SCLK edge after the rising edge of the
RFS signal causes DOUT to leave its high impedance state and
data is clocked out onto the DOUT line and also on subsequent
SCLK rising edges. The DOUT pin goes back into a high
impedance state on the 11th SCLK rising edge—Point “A” on
Figure 18. A minimum of 11 SCLKs are therefore needed to
carry out a serial read. Data on the DIN line is latched in on
the first SCLK falling edge after the falling edge of the TFS
signal and on subsequent SCLK falling edges. The control
register is updated on the 13th SCLK rising edge—point “B” on
Figure 18. A minimum of 13 SCLK pulses are therefore needed
to complete a serial write operation. In multipackage applications
the RFS and TFS signals can be used as chip select signals. The
serial interface will not shift data in or out until it receives the
active edge of the RFS or TFS signal.
Simplifying the Serial Interface
The five-wire interface is designed to support many different
serial interface standards. However, it is possible to reduce the
number of lines required to just three. By simply connecting the
TFS and RFS pins to the
CONVST signal (see Figure 4), the
CONVST signal can be used to enable the serial port for read-
ing and writing. This is only possible where a noncontinuous
serial clock is being used.
MICROPROCESSOR INTERFACING
The serial interface on the AD7811 and AD7812 allows the
parts to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7811 and AD7812 with some of the more common micro-
controller and DSP serial interface protocols.
AD7811/AD7812 to PIC16C6x/7x
The PIC16C6x Synchronous Serial Port (SSP) is configured as
an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
Figure 19 shows the hardware connections needed to interface
to the PIC16/17. In this example I/O port RA1 is being used to
pulse
CONVST and enable the serial port of the AD7811/
AD7812. This microcontroller transfers only eight bits of data
during each serial transfer operation; therefore, two consecutive
read/write operations are needed.
CONVST
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
PIC16C6x/7x*
SCK/RC3
SDO/RC5
SDI/ RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the PIC16/17
AD7811/AD7812 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 0), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 user manual. A connection diagram is shown in
CONVST
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
MC68HC11*
SCLK/PD4
MISO/PD2
MOSI/PD3
PA0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the MC68HC11
AD7811/AD7812 to 8051
The AD7811/AD7812 requires a clock synchronized to the
serial data. The 8051 serial interface must therefore be operated
in Mode 0. In this mode serial data enters and exits through
RxD and a shift clock is output on TxD (half duplex). Figure 21
shows how the 8051 is connected to the AD7811/AD7812.
However, because the AD7811/AD7812 shifts data out on the
rising edge of the shift clock and latches data in on the falling
edge, the shift clock must be inverted.
AD7811/AD7812*
DOUT
DIN
SCLK
TFS
8051*
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
RFS
Figure 21. Interfacing to the 8051 Serial Port
C
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