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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7808BR |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 22/28闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 10BIT 3.3V OCTAL 24-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Data Converter Fundamentals DAC Architectures |
| 妯欐簴鍖呰锛� | 31 |
| 瑷�(sh猫)缃檪闁擄細 | 1.5µs |
| 浣嶆暩(sh霉)锛� | 10 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 99mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 24-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 667k |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�鐣跺墠绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�
Parameter
B Grade1
Units
Comments
STATIC PERFORMANCE
MAIN DAC
Resolution
10
Bits
Relative Accuracy
卤4
LSB max
Gain Error
卤3
% FSR max
Bias Offset Error2
卤60
mV max
DAC Code = 0.5 Full Scale
Zero-Scale Error
卤35
mV max
DAC Code = 000H for Offset Binary
Monotonicity
9
Bits
and 200H for Twos Complement
Minimum Load Resistance
2
k
min
Coding
SUB DAC
Resolution
8
Bits
Differential Nonlinearity
卤0.125
LSB typ
Refers to an LSB of the Main DAC
卤0.5
LSB max
OUTPUT CHARACTERISTICS
Output Voltage Range3
VBIAS
卤 15/16 脳 V
BIAS
V
Twos Complement Coding
VBIAS/16 to 31/16
脳 V
BIAS
V
Offset Binary Coding
Voltage Output Settling Time to 10 Bits
4
s max
Typically 1.5
s
Slew Rate
2.5
V/
s typ
Digital-to-Analog Glitch Impulse
1
nV-s typ
1 LSB Change Around the Major Carry
Digital Feedthrough
0.5
nV-s typ
Digital Crosstalk
0.5
nV-s typ
Analog Crosstalk
卤0.2
LSB typ
DC Output Impedance
2
typ
Power Supply Rejection Ratio
0.002
%/% typ
V
DD
卤 10%
DAC REFERENCE INPUTS
REF IN Range
1.0 to VDD/2
V min to V max
REF IN Input Leakage
卤1
A max
Typically
卤1 nA
DIGITAL INPUTS
Input High Voltage, VIH @ VDD = 5 V
2.4
V min
Input High Voltage, VIH @ VDD = 3.3 V
2.1
V min
Input Low Voltage, VIL @ VDD = 5 V
0.8
V max
Input Low Voltage, VIL @ VDD = 3.3 V
0.6
V max
Input Leakage Current
卤10
A max
Input Capacitance
8
pF max
Input Coding
Twos Comp/Binary
REFERENCE OUTPUT
REF OUT Output Voltage
1.23
V nom
REF OUT Error
卤8
% max
REF OUT Temperature Coefficient
鈥�100
ppm/
掳C typ
REF OUT Output Impedance
5
k
nom
POWER REQUIREMENTS
VDD (AVDD and DVDD)
3/5.5
V min to V max
IDD (AIDD Plus DIDD)
Excluding Load Currents
Normal Mode
18
mA max
VIH = VDD, VIL = DGND
System Standby (SSTBY) Mode
250
A max
VIH = VDD, VIL = DGND
Power-Down (
PD) Mode
@ +25
掳C1
A max
VIH = VDD, VIL = DGND
TMIN鈥揟MAX
3
A max
Power Dissipation
Excluding Power Dissipated in Load
Normal Mode
99
mW max
System Standby (SSTBY) Mode
1.38
mW max
Power-Down (
PD) Mode
@ +25
掳C
5.5
W max
TMIN鈥揟MAX
16.5
W max
NOTES
1Temperature range is 鈥� 40
掳C to +85掳C.
2Can be minimized using the Sub DAC.
3V
BIAS is the center of the output voltage swing and can be VDD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.
Specifications subject to change without notice.
(AVDD and DVDD = 3.3 V
10% to 5 V
10%; AGND = DGND = 0 V;
Reference = Internal Reference; CL = 100 pF; RL = 2 k
to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)
AD7808/AD7809鈥揝PECIFICATIONS
AD7804/AD7805/AD7808/AD7809
REV. A
鈥�3鈥�
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