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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7808BR-REEL |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 10BIT OCTAL SRL 24-SOIC |
| 鐢㈠搧鍩硅〒妯″锛� | Data Converter Fundamentals DAC Architectures |
| 妯欐簴鍖呰锛� | 1,000 |
| 瑷疆鏅傞枔锛� | 1.5µs |
| 浣嶆暩(sh霉)锛� | 10 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞夋彌鍣ㄦ暩(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 99mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 24-SOIC W |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 667k |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�鐣跺墠绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�
AD7804/AD7805/AD7808/AD7809
REV. A
鈥�4鈥�
(VDD = 3.3 V
10% to 5 V
10%; AGND = DGND = 0 V; Reference =
Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
Limit at TMIN, TMAX
Parameter
All Versions
Units
Description
t1
100
ns min
CLKIN Cycle Time
t2
40
ns min
CLKIN High Time
t3
40
ns min
CLKIN Low Time
t4
30
ns min
FSIN Setup Time
t5
30
ns min
Data Setup Time
t6
5
ns min
Data Hold Time
t6A
6
ns min
LDAC Hold Time
t7
90
ns max
FSIN Hold Time
20
ns min
t8
40
ns min
LDAC, CLR Pulsewidth
t9
100
ns min
LDAC Setup Time
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.
Specifications subject to change without notice.
CLKIN(I)
FSIN(I)
SDIN(I)
DB15
t
2
t
3
t
7
t
8
CLR
LDAC1
t
5
t
6A
t
1
t
9
t
8
t
4
t
5
t
6
DB0
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
LDAC2
Figure 1. Timing Diagram for AD7804 and AD7808
AD7804/AD7808 TIMING CHARACTERISTICS1
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-24R-IV-F3 | CONVERTER MOD DC/DC 7.5V 150W |
| VI-J6M-MW-S | CONVERTER MOD DC/DC 10V 100W |
| SY88345BLEY | IC POST AMP 3.3V 3.2GBPS 10-MSOP |
| VI-J6K-MW-S | CONVERTER MOD DC/DC 40V 100W |
| VI-J5D-MW-S | CONVERTER MOD DC/DC 85V 100W |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7808BRZ | 鍔熻兘鎻忚堪:IC DAC 10BIT OCTAL SRL 24-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁鎻涘櫒 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:50 绯诲垪:- 瑷疆鏅傞枔:4µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞夋彌鍣ㄦ暩(sh霉)鐩�:2 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:8-uMAX 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:2 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鐢㈠搧鐩寗闋侀潰:1398 (CN2011-ZH PDF) |
| AD7808BRZ-REEL | 鍔熻兘鎻忚堪:IC DAC 10BIT OCTAL SRL 24-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁鎻涘櫒 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Data Converter Fundamentals DAC Architectures 妯欐簴鍖呰:750 绯诲垪:- 瑷疆鏅傞枔:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳鍟嗚ō鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
| AD7808BST | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:+3.3 V to +5 V Quad/Octal 10-Bit DACs(300.12 k) |
| AD7809 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:+3.3 V to +5 V Quad/Octal 10-Bit DACs |
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