參數(shù)資料
型號： AD7799BRU
廠商： Analog Devices Inc
文件頁數(shù)： 7/28頁
文件大?。?/td> 0K
描述： IC ADC 24BIT 3CH LP 16-TSSOP
標準包裝： 1
位數(shù)： 24
采樣率（每秒）： 470
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 2.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極
配用： EVAL-AD7799EBZ-ND - BOARD EVALUATION FOR AD7799
其它名稱： Q2161119
Data Sheet
AD7798/AD7799
Rev. B | Page 15 of 28
Table 13. Operating Modes
MD2
MD1
MD0
Mode
0
Continuous-Conversion Mode (Default). In continuous-conversion mode, the ADC continuously performs conversions
and places the result in the data register. RDY goes low when a conversion is complete. After power-on, a channel
change, or a write to the mode, configuration, or IO registers, the first conversion is available after a period of 2/fADC,
and subsequent conversions are available at a frequency of fADC.
0
1
Single-Conversion Mode. When single-conversion mode is selected, the ADC powers up and performs a single
conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes
a time of 2/fADC. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-
down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or
another conversion is performed.
0
1
0
Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are
still provided.
0
1
Power-Down Mode. In this mode, all AD7798/AD7799 circuitry is powered down, including the burnout currents.
1
0
Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration
takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the
calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is
placed in the offset register of the selected channel.
1
0
1
Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for
this calibration. When the gain equals 1, a calibration takes two conversion cycles to complete. For higher gains, four
conversion cycles are required to perform the full-scale calibration. RDY goes high when the calibration is initiated
and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The
measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale
calibrations cannot be performed when the gain equals 128. The ADC is factory-calibrated at a gain of 128 and this
factory-generated value is placed in the full-scale register on power up and when the gain is set to 128. With this
gain setting, a system full-scale calibration can be performed. To minimize the full-scale error, a full-scale calibration
is required each time the gain of a channel is changed.
1
0
System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins as
selected by the CH2 to CH0 bits. A system offset calibration takes two conversion cycles to complete. RDY goes high
when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode
following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A
zero-scale calibration is required each time the gain of a channel is changed.
1
System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins, as selected
by the CH2 to CH0 bits. A calibration takes two conversion cycles to complete. RDY goes high when the calibration
is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.
The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration
is required each time the gain of a channel is changed.
Table 14. Update Rates Available
FS3
FS2
FS1
FS0
fADC (Hz)
tSETTLE (ms)
Rejection @ 50 Hz/60 Hz
0
Reserved
0
1
470
4
0
1
0
242
8
0
1
123
16
0
1
0
62
32
0
1
0
1
50
40
0
1
0
39
48
0
1
33.2
60
1
0
19.6
101
90 dB (60 Hz only)
1
0
1
16.7
120
80 dB (50 Hz only)
1
0
1
0
16.7
120
65 dB
1
0
1
12.5
160
66 dB
1
0
10
200
69 dB
1
0
1
8.33
240
70 dB
1
0
6.25
320
72 dB
1
4.17
480
74 dB
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