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參數(shù)資料
| 型號(hào)： | AD7791BRM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Power, Buffered 24-Bit Sigma-Delta ADC |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MSOP-10 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 308K |
| 代理商： | AD7791BRM-REEL |
AD7791
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
Rev. 0 | Page 11 of 20
SR7
RDY(1)
SR6
ERR(0)
SR5
0(0)
SR4
0(0)
SR3
1(1)
SR2
WL(1)
SR1
CH1(0)
SR0
CH0(0)
Table 8. Status Register Bit Designations
Bit Location
Bit Name
SR7
RDY
Description
Ready bit for ADC.
Cleared
when data is written to the ADC data register. The RDY bit is
set
automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also
set
when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit.
Set
to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange.
Cleared
by a write operation to start a conversion.
This bit is automatically
cleared
.
This bit is automatically
cleared
.
This bit is automatically
set
.
This bit is automatically
set
if the device is an AD7791. It can be used to distinguish between the AD7791
and AD7790, in which the bit is
cleared
.
These bits indicate which channel is being converted by the ADC.
SR6
ERR
SR5
SR4
SR3
SR2
0
0
1
1
SR1–SR0
CH1–CH0
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit desig-
nations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes
the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup regis-
ter resets the modulator and filter and sets the RDY bit.
MR7
MD1(0)
MR6
MD0(0)
MR5
0(0)
MR4
0(0)
MR3
BO(0)
MR2
U/B(0)
MR1
BUF(1)
MR0
0(0)
Table 9. Mode Register Bit Designations
Bit Location
Bit Name
MR7–MR6
MD1–MD0
Description
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. RDY goes low when a conversion is complete. The user can read these
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ f
ADC
while subsequent conversions are available at a frequency of f
ADC
. In single
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up and performs a single conversion, which
occurs after a period 2/f
ADC
. The conversion result in placed in the data register, RDY goes low, and the
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active
(low) until the data is read or another conversion is performed. See Table 10.
This bit must be programmed with a Logic 0 for correct operation.
MR5–MR4
0
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