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參數(shù)資料
| 型號： | AD7787BRM-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT LP 2CH SIG 10-MSOP |
| 標準包裝： | 3,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 225µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
Data Sheet
AD7787
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed
from a voltage level of 1.6 V (see Figure 3 and Figure 4).
VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK High Pulse Width
t4
100
ns min
SCLK Low Pulse Width
Read Operation
t1
0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
0
ns min
SCLK Active Edge to Data Valid Delay2
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
10
ns min
Bus Relinquish Time after CS Inactive Edge
80
ns max
t6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t8
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time2
t9
30
ns min
Data Valid to SCLK Edge Setup Time
t10
25
ns min
Data Valid to SCLK Edge Hold Time
t11
0
ns min
CS Rising Edge to SCLK Edge Hold Time
1
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
2
The SCLK active edge is the falling edge of SCLK.
3
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
4
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
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