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參數(shù)資料
| 型號： | AD7781CRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT 1CH LP SD 16TSSOP |
| 設計資源： | Weigh Scale Design Using AD7781 with Internal PGA (CN0108) |
| 標準包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 16.7 |
| 數(shù)據接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
AD7781
Rev. 0 | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD7781
TOP VIEW
(Not to Scale)
NC = NO CONNECT
1
2
3
4
5
6
7
8
SCLK
DOUT/RDY
NC
AIN(–)
AIN(+)
GAIN
NC
REFIN(+)
16
15
14
13
12
11
10
9
FILTER
PDRST
DVDD
BPDSW
REFIN(–)
GND
AVDD
NC
SCLK 1
DOUT/RDY 2
NC 3
GAIN 4
FILTER
14
PDRST
13
DVDD
12
AVDD
11
AIN(+) 5
GND
10
AIN(–) 6
BPDSW
9
AD7781
TOP VIEW
(Not to Scale)
REFIN(+) 7
REFIN(–)
8
NC = NO CONNECT
0
81
62
-0
06
08
16
2-
00
7
Figure 6. SOIC Pin Configuration
Figure 7. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOIC
TSSOP
Mnemonic
Description
1
2
SCLK
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt-
triggered input. The serial clock can be active only when transferring data from the AD7781. The data
from the AD7781 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous
during the data transfer, with the information being transmitted from the ADC in smaller data batches.
2
3
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose: as a data ready pin, going low
to indicate the completion of a conversion, and as a serial data output pin to access the data register of
the ADC. Eight status bits accompany each data read (see
). The DOUT/
RDY falling edge can be
used as an interrupt to a processor, indicating that new data is available. If the data is not read after the
conversion, the pin goes high before the next update occurs. The serial interface is reset each time that a
conversion is available. Therefore, the user must ensure that any conversions being transmitted are
completed before the next conversion is available.
3
1, 4, 16
NC
No Connect. This pin can be left floating.
4
5
GAIN
Gain Select Pin. When GAIN is low, the gain is set to 128. When GAIN is high, the gain is set to 1.
5
6
AIN(+)
Analog Input. AIN(+) is the positive terminal of the differential analog input pair, AIN(+)/AIN().
6
7
AIN()
Analog Input. AIN() is the negative terminal of the differential analog input pair, AIN(+)/AIN().
7
8
REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(). The nomi-
nal reference voltage (REFIN(+) REFIN()) is 5 V, but the part can function with a reference of 0.5 V to AVDD.
8
9
REFIN()
Negative Reference Input.
9
10
BPDSW
Bridge Power-Down Switch to GND. When PDRST is high, the bridge power-down switch is closed.
When PDRST is low, the switch is opened.
10
11
GND
Ground Reference Point.
11
12
AVDD
Supply Voltage, 2.7 V to 5.25 V.
12
13
DVDD
Digital Interface Supply Voltage. The logic levels for the serial interface pins and the digital control pins
are related to this supply, which is between 2.7 V and 5.25 V. The DVDD voltage is independent of the
voltage on AVDD; therefore, AVDD can equal 5 V with DVDD at 3 V or vice versa.
13
14
PDRST
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode, and the low-side power
switch is opened. All the logic on the chip is reset, and the DOUT/RDY pin is tristated. When PDRST is high,
the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC contin-
uously converts. In addition, the low-side power switch is closed. The internal clock requires approximately
1 ms to power up.
14
15
FILTER
Filter Select Pin. When FILTER is low, the fast settling filter is selected. The update rate is set to 16.7 Hz,
which gives a filter settling time of 120 ms. When FILTER is high, the high rejection filter is selected. The
update rate is set to 10 Hz, which gives a filter settling time of 300 ms. With this filter, the stop-band
(higher than fADC) attenuation is better than 45 dB.
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