參數(shù)資料
型號(hào): AD7742
廠商: Analog Devices, Inc.
英文描述: Low Cost, Single & Multi-Channel,Voltage-to-Frequency Converters(低成本,多通道,電壓-頻率轉(zhuǎn)換器)
中文描述: 低成本,單
文件頁(yè)數(shù): 7/9頁(yè)
文件大小: 304K
代理商: AD7742
AD7741/42
Prelim J1 7/98
7
Preliminary Technical Data
Analog Input Channel 2. This is either a pseudo-differential input with respect to IN4 or it is the
negative input of a differential analog input pair when used with IN1 (See Table I).
Analog Input Channel 3. This is the positive input of a differential analog input pair when used
with IN4 (See Table I).
Analog Input Channel 4. This is either the common input for pseudo-differential inputs on IN1
and IN2 or it is the negative input of a analog input pair when used with IN3 (See Table I).
Gain Select Input. This is used as a gain select input for the PGA to select one of two gains for the
PGA.
AD7742 PIN FUNCTION DESCRIPTION
Pin
No.
Pin
Mnemonic
Description
F
OUT
V
DD
GND
A1
Frequency Output
Positive supply voltage, +5 V ± 5%.
Analog Ground.
Channel Select Input. This is used as a channel select input in conjunction with A0 to select one
of four possible input channel configurations allowable.
A0
Channel Select Input. This is used as a channel select input in conjunction with A1 to select one
of four possible input channel configurations allowable.
External Clock Output. When the master clock for the device is a crystal, the crystal is connected
between CLKIN and CLKOUT. When an external clock is applied to CLKIN, CLKOUT pro-
vides an inverted clock signal. This clock must be buffered before being used to provide a clock
source for a microprocessor, ADC or other system components.
External Clock Input. The master clock for the device can be provided in the form of a crystal or
an external clock. A crystal can be tied across the CLKIN, CLKOUT pins. Alternately, the
CLKIN pin can be driven with a CMOS-compatible clock and CLKOUT left unconnected. The
frequency on CLK IN can be as high as 5MHz.
Unipolar/
BIPOLAR
Input Select. This pin determines whether the device is to operate with differ-
ential bipolar input signals (common mode range: -300mV to (V
-2V)) or whether the differential
analog input signals are always positive. With UNI/
BIP
high, a differential analog input signal
equal to 0 V results in an output frequency of F
min (5% of F
) and an input of REF IN/
Gain results in an output frequency of F
max (45% of F
). With UNI/
BIP
low, a differential
analog input signal of -REF IN/Gain results in an output frequency of F
min (5% of F
CLOCK
)
and an input of +REF IN/Gain results in an output frequency of F
OUT
max (45% of F
CLOCK
Voltage Reference Output. A +2.5V reference is provided at this pin. This reference can be tied
directly to REF IN. It can also be used to drive external circuitry if it is buffered first.
Voltage Reference Input. This defines the span of the VFC. For specified operation a +2.5 V ref-
erence is required at this pin. It can be tied to REF OUT directly or, if a precision reference is
available, it can be applied to this pin.
CLKOUT
CLKIN
UNI/
BIP
REFOUT
REFIN
IN1
Analog Input Channel 1. This is either a pseudo-differential input with respect to IN4 or it is the posi
tive input of a differential analog input pair when used with IN2 (See Table I). In bipolar mode the
differential analog input voltage range is ±REF IN /Gain of the PGA. In unipolar mode the differential
analog input voltage range is 0 to +REF IN /Gain.
IN2
IN3
IN4
G0
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