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參數(shù)資料
| 型號： | AD773AJD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 20 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 223K |
| 代理商： | AD773AJD |
AD773A
REV. 0
–3–
AC SPECIFICATIONS
AD773AJ
T yp
AD773AK
T yp
Parameter
Min
Max
Min
Max
Units
DYNAMIC PERFORMANCE
1
Signal-to-Noise plus Distortion
(S/N+D) Ratio
f
IN
= 1 MHz
f
IN
= 10 MHz
Effective Number of Bits (ENOB)
f
IN
= 1 MHz
f
IN
= 10 MHz
T otal Harmonic Distortion (T HD)
f
IN
= 1 MHz
f
IN
= 10 MHz
Spurious Free Dynamic Range
2
Full Power Bandwidth
Intermodulation Distortion (IMD)
3
Second Order Products
T hird Order Products
Differential Phase
Differential Gain
T ransient Response
Overvoltage Recovery T ime
52
50
56
54
54
51
56
54
dB
dB
9.0
8.7
9.0
8.7
Bits
Bits
–67
–65
70
100
–57
–54
–67
–65
70
100
–59
–55
dB
dB
dB
MHz
–69
–64
0.2
0.5
25
25
–69
–64
0.2
0.5
25
25
dB
dB
Degree
%
ns
ns
NOT ES
1
For typical dynamic performance curves at f
SAMPLE
= 20 Msps see Figures 2 through 7.
2
f
= 1 MHz.
3
fa = 1.0 MHz, fb = 1.05 MHz.
Specifications subject to change without notice.
TIMNGSPECIFICATIONS
Symbol
Min
T yp
Max
Units
Conversion Rate
Clock Period
Clock High
Clock Low
Output Delay
Aperture Delay
Aperture Jitter
Pipeline Delay (Latency)
20
Msps
ns
ns
ns
ns
ns
ps
Clock Cycles
t
CLK
t
CH
t
CL
t
OD
50
24.5
24.5
20
7
9
4
DATA
N
DATA
N+1
VIN
CLOCK
BIT 1–10
MSB, OTR
N
N+1
N
N+1
t
C
t
CH
t
CL
t
OD
Figure 1. AD773A Timing Diagram
(T
MN
to T
MAX
wth AV
DD
= +5 V
6
5%, AV
SS
= –5 V
6
5%, DV
DD
, = +5 V
6
5%, DRV
DD
= +5 V
6
5%,
V
REF
= +2.500 V unless otherwse noted, f
SAMPLE
= 20 MSPS, f
lN
amplitude = –0.5 dB)
(for all grades T
MN
to T
MAX
wth AV
DD
= +5 V
6
5%, AV
SS
= –5 V
6
5%, DV
DD
= +5 V
6
5%,
DRV
DD
= +5 V
6
5%, V
REF
= +2.500 V unless otherwse noted, f
SAMPLE
= 20 MSPS)
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD773AKD | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 20 MSPS Monolithic A/D Converter |
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| AD773JD | 制造商:Analog Devices 功能描述: |
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