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參數(shù)資料
型號(hào)： AD7732BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 2CH SIG-DEL 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
配用： EVAL-AD7732EBZ-ND - BOARD EVAL FOR AD7732
AD7732
Rev. A | Page 5 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Power Dissipation (Normal Mode) 14
85
100
mW
AVDD+DVDD Current (Standby Mode)15
140
μA
Power Dissipation (Standby Mode)15
750
μW
1 Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.
3 VCM = Common-Mode Voltage = 0 V.
4 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
5 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
6 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.
7 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.
8 The AIN absolute voltage of ±16.5 V applies for a nominal VBIAS voltage of +2.5 V. By configuring the BIAS and RA to RD pins differently, the part will work with higher
AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AVDD – 300 mV. Absolute voltage for the AIN,
BIAS, and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings.
9 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ.
10 For specified performance. Part is functional with lower VREF.
11 Dynamic current charging the sigma-delta modulator input switching capacitor.
12 Outside the specified calibration range, calibration is possible but the performance may degrade.
13 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
14 With external MCLK, MCLKOUT is disabled (the CLKDIS bit is set in the mode register).
15 External MCLKIN = 0 V or DVDD, Digital Inputs = 0 V or DVDD, and P0 and P1 = 0 V or AVDD.
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AD7734BRU-REEL 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 3.05Msps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel
AD7734BRU-REEL7 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 3.05Msps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel
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