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參數(shù)資料
| 型號： | AD7731BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.4k |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–14–
REV. 0
Bit
Location
Mnemonic
Description
CR3
ZERO
A zero must be written to this bit to ensure correct operation of the AD7731.
CR2-CR0
RS2-RS0
Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which
one of eight on-chip registers the next read or write operation takes place as shown in Table VIII.
Table VIII. Register Selection
RS2
RS1
RS0
Register
0
Communications Register (Write Operation)
0
Status Register (Read Operation)
0
1
Data Register
0
1
0
Mode Register
0
1
Filter Register
1
0
No Register Access
1
0
1
Offset Register
1
0
Gain Register
1
Test Register
Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de-
notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets
indicates the power-on/reset default status of that bit.
Table IX. Status Register
7
R
S6
R
S5
R
S4
R
S3
R
S2
R
S1
R
S0
R
S
Y
D
R
)
1
(
Y
D
T
S
)
1
(
)
0
(
Y
B
T
S)
0
(
F
E
R
O
N)
X
(
3
S
M)
X
(
2
S
M)
X
(
1
S
M)
X
(
0
S
M
Bit
Location
Mnemonic
Description
SR7
RDY
Ready Bit. This bit provides the status of the
RDY flag from the part. The status and func-
tion of this bit is the same as the
RDY output pin. A number of events set the RDY bit high
as indicated in Table XVII.
SR6
STDY
Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter
is in FASTStep mode (see Filter Register section), and responding to a step input, the
STDY bit remains high as the initial conversion results become available. The RDY output
and bit are set low on these initial conversions to indicate that a result is available. However,
if the
STDY is high, it indicates that the result being provided is not from a fully settled
second-stage FIR filter. When the FIR filter has fully settled, the
STDY bit will go low coin-
cident with
RDY. If the part is never placed into its FASTStep mode, the STDY bit will go
low at the first Data Register read and it is not cleared by subsequent Data Register reads.
A number of events set the
STDY bit high as indicated in Table XVII. STDY is set high
along with
RDY by all events in the table except a Data Register read.
SR5
STBY
Standby Bit. This bit indicates whether the AD7731 is in its Standby Mode or normal mode
of operation. The part can be placed in its standby mode using the
STANDBY input pin or
by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of
this bit is 0 assuming the
STANDBY pin is high.
SR4
NOREF
No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V
or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on
completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on
completion of a calibration, updating of the calibration registers is inhibited.
SR3-SR0
MS3-MS0
These bits are for factory use. The power-on/reset status of these bits varies depending on the
factory-assigned number.
REV. A
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