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參數資料
| 型號： | AD7731BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | MS-001, PLASTIC, DIP-24 |
| 文件頁數： | 28/44頁 |
| 文件大?。?/td> | 411K |
| 代理商： | AD7731BN |
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AD7731
–28–
REV. 0
FAST
Step Mode (SK IP = 0, FAST = 1)
T he second mode of operation of the second stage filter is in
FAST
Step mode which enables it to respond rapidly to step
inputs even when the second stage filter is in the loop. T he
FAST
Step mode is not relevant with SK IP mode enabled.
T he
FAST
Step mode is enabled by placing a 1 in the FAST
bit of the Filter Register. If the FAST bit is 0, the part continues
to process step inputs with the normal FIR filter as the second
stage filter. With
FAST
Step mode enabled, the second stage
filter will continue to process steady state inputs with the filter
in its normal FIR mode of operation. However, the part is con-
tinuously monitoring the output of the first stage filter and com-
paring it with the second-previous output. If the difference
between these two outputs is greater than a predetermined
threshold (1% of full scale), the second stage filter switches to a
simple moving average computation. T his also happens when a
change in channels takes place regardless of how close the volt-
ages on the two channels are. When the change is detected, the
STDY
bit of the Status Register goes to 1.
T he initial number of averages in the moving average computa-
tion is either 2 (chop enabled) or 1 (chop disabled). T he num-
ber of averages will be held at this value as long as the threshold
is exceeded. Once the threshold is no longer exceeded (the step
on the analog input has settled), the number of outputs used to
compute the moving average output is increased. T he first and
second outputs from the first stage filter where the threshold is
no longer exceeded is computed as an average by 2, then 4
outputs with an average of 4, 8 outputs with an average of 8 and
6 outputs with an average of 16. At this time, the second stage
filter reverts back to its normal FIR mode of operation. When
the second stage filter reverts back to the normal FIR, the
STDY
bit of the Status Register goes to 0.
Figure 13 gives an indication of the different responses to a step
input with
FAST
Step mode enabled and disabled. T he verti-
cal axis indicates the settling of the output to the input step
change while the horizontal axis shows how many outputs it
takes for that settling to occur. T he positive input step change
occurs at a time coincident with the fifth output.
NUMBER OF OUTPUTS
20000000
15000000
00
25
5
C
10
15
20
10000000
5000000
Figure 13. Step Response for FASTStep and Normal
Operation
In
FAST
Step mode, the part has settled to the new value
much faster. For example, with CHP = 1, the
FAST
Step
mode settles to its value in two outputs while the normal mode
settling takes 23 outputs. Between the second and 23rd output,
the
FAST
Step mode produces a settled result but with addi-
tional noise compared to the specified noise level for its operat-
ing conditions. T his noise level starts at approximately 3 times
the final noise converging to FIR mode performance. T he com-
plete settling time to where the part is back within the specified
noise number, is the same for
FAST
Step mode and for normal
mode. When switching channels, the profile of Figure 13 will
not be seen. Since the part is synchronized when a channel
change takes place, it will not produce an output until the filter
(either
FAST
Step or FIR) is settled. T able X VIII gives an
indication of the faster settling time benefits of
FAST
Step
mode.
As can be seen from T able X VIII, the
FAST
Step mode gives
a much earlier indication of where the output channel is going
and what its new value is. T his feature is very useful in scanning
multiple channels where the user does not have to wait for the
FIR settling time to see if a channel has changed value. In this
case, the part can be set up with CHP = 1, SK IP = 0 and FAST
= 1. T his takes advantage of the low drift, better noise immunity
benefits of the CHOP mode. When a change in channels takes
place, the part enters
FAST
Step mode and provides an output
result in 2
×
1/Output Rate.
Note, if the FAST bit is set and the part operated in single con-
version mode, the AD7731 will continue to output results until
the
STDY
bit goes to 0.
T able X VIII. T ime to First and Subsequent Outputs Follow-
ing Channel Change
T ime
to First O/P
1
T ime to
Subsequent O/Ps
SKIP
CHP
FAST
0
0
1
1
0
0
0
1
0
1
0
1
0
0
X
2
X
1
1
24
×
SF/f
MOD
66
×
SF/f
MOD
3
×
SF/f
MOD
3
×
SF/f
MOD
3
×
SF/f
MOD
6
×
SF/f
MOD
SF/f
MOD
3
×
SF/f
MOD
SF/f
MOD
3
×
SF/f
MOD
SF/f
MOD
3
×
SF/f
MOD
1
T his O/P is fully settled.
2
X = Don’t Care.
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