參數(shù)資料
型號(hào): AD7714ARZ-3REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 31/40頁(yè)
文件大小: 0K
描述: IC ADC 24BIT SIGMA-DELTA 24SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 1k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 7mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 3 個(gè)差分,單極;3 個(gè)差分,雙極;5 個(gè)偽差分,單極;5 個(gè)偽差分,雙極
配用: EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
2
AD7714
REV. C
–37–
Data Acquisition
The AD7714 with its three differential channels (or five pseudo-
differential channels) is suited to low bandwidth, high resolution
data acquisition systems. In addition, the three-wire digital
interface allows this data acquisition front end to be isolated
with just three optoisolators. The entire system can be operated
from a single +3 V or +5 V supply provided that the input sig-
nals to the AD7714’s analog inputs are all of positive polarity.
The low power operation of the AD7714 ensures that very little
power has to be brought across the isolation barrier. Figure 15
shows the AD7714 in an isolated data acquisition system.
CLOCK
GENERATION
CHARGE BALANCING A/D
CONVERTER
DIGITAL
FILTER
AVDD
1 A
BUFFER
AVDD
SERIAL INTERFACE
REGISTER BANK
STANDBY
SYNC
MCLK IN
MCLK OUT
1 A
REF IN (+)
REF IN (–)
AGND
DGND
BUFFER
DOUT
DIN
CS
SCLK
POL
DRDY
RESET
DVDD
AD7714
DVDD
GND
+5V
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
VOUT
AD780
+5V
+VIN
A = 1–128
AGND
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
MICROCONTROLLER
OPTO-ISOLATORS
SWITCHING
MATRIX
PGA
AUTO-ZEROED
MODULATOR
Figure 15. Data Acquisition System Using the AD7714
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