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參數(shù)資料
| 型號(hào)： | AD7714ARSZ-5REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極 |
| 配用： | EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714 |
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2
AD7714
REV. C
–17–
Filter Registers. Power On/Reset Status: Filter High Register: 01 Hex. Filter Low Register: 40 Hex.
There are two 8-bit Filter Registers on the AD7714 from which data can either be read or to which data can be written. Tables IX
and X outline the bit designations for the Filter Registers.
Table IX. Filter High Register (RS2–RS0 = 0, 1, 0)
B/U
WL
BST
ZERO
FS11
FS10
FS9
FS8
A Versions
B/U
WL
BST
CLKDIS
FS11
FS10
FS9
FS8
Y Versions
Table X. Filter Low Register (RS2–RS0 = 0, 1, 1)
FS7
FS6
FS5
FS4
FS3
FS2
FS1
FS0
All Versions
B/U
Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or RESET)
status of this bit. A 1 in this bit selects unipolar operation.
WL
Word Length. A 0 in this bit selects 16-bit word length when reading from the data register (i.e.,
DRDY returns
high after 16 serial clock cycles in the read operation). This is the default (Power-On or RESET) status of this
bit. A 1 in this bit selects 24-bit word length.
BST
Current Boost. A 0 in this bit reduces the current taken by the analog front end. When the part is operated with
fCLK IN = 1 MHz or at gains of 1 to 4 with fCLK IN = 2.4576 MHz, this bit should be 0 to reduce the current
drawn from AVDD, although the device will operate just as well with this bit at a 1. When the AD7714 is oper-
ated at gains of 8 to 128 with fCLK IN = 2.4576 MHz, this bit must be 1 to ensure correct operation of the
device. The Power-On or RESET status of this bit is 0.
ZERO
To ensure correct operation of the A Versions of the part, a 0 must be written to this bit.
CLKDIS
Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLKOUT
pin. When disabled, the MCLKOUT pin is forced low. This feature allows the user the flexibility of using the
MCLKOUT as a clock source for other devices in the system or for turning off the MCLKOUT as a power
saving feature. When using an external master clock or the MCLKIN pin, the AD7714 continues to have inter-
nal clocks and will convert normally with its CLKDIS bit active. When using a crystal oscillator or ceramic
resonator across the MCLK IN or MCLKOUT pins, the AD7714 clock is stopped and no conversions take
place when the CLKDIS bit is active.
FS11–FS0
Filter Selection. The on-chip digital filter provides a Sinc3 (or (Sinx/x)3 ) filter response. The 12 bits of data
programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter and
the data rate for the part. In association with the gain selection, it also determines the output noise (and hence
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship:
filter first notch frequency = (fCLK IN/128)/code
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 4,000. With the
nominal fCLK IN of 2.4576 MHz, this results in a first notch frequency range from 4.8 Hz to 1.01 kHz. To
ensure correct operation of the AD7714, the value of the code loaded to these bits must be within this range.
Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I through IV show
the effect of the filter notch frequency and gain on the effective resolution of the AD7714. The output data rate
(or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For
example, if the first notch of the filter is selected at 50 Hz then a new word is available at a 50 Hz rate or every
20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.
The settling time of the filter to a full-scale step input change is worst case 4
× 1/(output data rate). For
example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is
80 ms max. This settling time can be reduced to 3
× 1/(output data rate) by synchronizing the step input
change to a reset of the digital filter. In other words, if the step input takes place with the
SYNC input low or
the FSYNC bit high, the settling time will be 3
× 1/(output data rate) from when SYNC returns high or
FSYNC returns low. If a change of channel takes place, the settling time is 3
× 1/(output data rate) regardless of
the
SYNC or FSYNC status as the part issues an internal SYNC command when requested to change channels.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262
× filter first notch frequency.
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