- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10306 > AD7709BRUZ-REEL7 (Analog Devices Inc)IC ADC 16BIT SIGMA-DELTA 24TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7709BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 105 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.75mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極；2 個(gè)差分，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
REV. A
AD7709
–15–
Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H)
The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the
Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on-reset default status of that bit.
Table VI. Status Register Bit Designations
Bit
Location
Name
Description
SR7
RDY
Ready Bit for ADC.
Set when data is written to the ADC data register.
The RDY bit is cleared automatically after the ADC data register has been read or a period of time before
the data register is updated with a new conversion result.
SR6
0This bit is automatically cleared.
SR5
0This bit is automatically cleared.
SR4
0This bit is automatically cleared.
SR3
ERR
ADC Error Bit. This bit is set at the same time as the RDY bit.
Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.
Error sources include Overrange, Underrange.
Cleared by a write to the mode bits to initiate a conversion.
SR2
0This bit is automatically cleared.
SR1
STBY
Standby Bit Indication.
When this bit is set, the AD7709 is in power-down mode.
This bit is cleared when the ADC is powered up.
SR0
LOCK
PLL Lock Status Bit.
Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact
sampling frequencies, etc., the LOCK bit should be interrogated and the result discarded if the LOCK
bit is 0.
7
R
S6
R
S5
R
S4
R
S3
R
S2
R
S1
R
S0
R
S
)
0
(
Y
D
R)
0
(
0)
0
(
0)
0
(
0)
0
(
R
E)
0
(
0)
0
(
Y
B
T
S)
0
(
K
C
O
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27467T21B11B | CONN HSG PLUG 11POS STRGHT SCKT |
| VI-BN0-IX-B1 | CONVERTER MOD DC/DC 5V 75W |
| D38999/20WG75AN | CONN HSG RCPT 4POS WALL MT PINS |
| VI-BN0-IW-B1 | CONVERTER MOD DC/DC 5V 100W |
| VI-2NV-CU-S | CONVERTER MOD DC/DC 5.8V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD770JD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| AD770KD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| AD770SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| AD7710 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Signal Conditioning ADC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。