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參數資料
| 型號： | AD7708BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 4/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT R-R 8/10CH 28-TSSOP |
| 標準包裝： | 50 |
| 位數： | 16 |
| 采樣率（每秒）： | 1.37k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 3.84mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 4 個差分，單極；4 個差分，雙極；8 個偽差分，單極；8 個偽差分，雙極 |
| 配用： | EVAL-AD7708EBZ-ND - BOARD EVAL FOR AD7708 |
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REV. 0
–12–
AD7708/AD7718
PIN FUNCTION DESCRIPTIONS
Pin No
Mnemonic
Function
1
AIN7
Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN8. (See ADC Control Register section.)
2
AIN8
Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN7. (See ADC Control Register section.)
3AVDD
Analog Supply Voltage
4
AGND
Analog Ground
5
REFIN1(–)
Negative Reference Input. This reference input can lie anywhere between AGND and AVDD – 1 V.
6
REFIN1(+)
Positive reference input. REFIN(+) can lie anywhere between AVDD and AGND. The nominal
reference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a reference
range from 1 V to AVDD.
7
AIN1
Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN2. (See ADC Control Register Section.)
8
AIN2
Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN1. (See ADC Control Register section.)
9
AIN3
Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN4. (See ADC Control Register section.)
10
AIN4
Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN3. (See ADC Control Register section.)
11
AIN5
Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN6. (See ADC Control Register section ADCCON.)
12
AINCOM
All analog inputs are referenced to this input when configured in pseudo-differential input mode.
13
REFIN2(+)/AIN9
Positive reference input/analog input. This input can be configured as a reference input with the
same characteristics as REFIN1(+) or as an additional analog input. When configured as an
analog input this pin provides a programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN10. (See ADC Control Register section.)
14
REFIN2(–)/AIN10
Negative reference input/analog input. This pin can be configured as a reference or analog input.
When configured as a reference input it provides the negative reference input for REFIN2.
When configured as an analog input it provides a programmable-gain analog input that can be
used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-
differential input pair when used with AIN9. (See ADC Control Register section.)
15
AIN6
Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN5. (See ADC Control Register section.)
16
P2
P2 can act as a general-purpose Input/Output bit referenced between AVDD and AGND. There
is a weak pull-up to AVDD internally on this pin.
17
AGND
It is recommended that this pin be tied directly to AGND.
18
P1
P1 can act as a general-purpose Input/Output bit referenced between AVDD and AGND. There
is a weak pull-up to AVDD internally on this pin.
19
RESET
Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-up
internally to DVDD.
20
SCLK
Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-trigger
input making an opto-isolated interface more robust. The serial clock can be continuous with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock
with the information being transmitted to or from the AD7708/AD7718 in smaller batches of data.
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