參數(shù)資料
型號(hào)： AD7707BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
中文描述： 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20
封裝： LOW PROFILE, TSSOP-20
文件頁數(shù)： 3/40頁
文件大?。?/td> 316K
代理商： AD7707BRU
REV. A
–3–
AD7707
Parameter
B Version
1
Units
Conditions/Comments
HIGH LEVEL ANALOG INPUT CHANNEL (AIN3)
AIN3 Voltage Range
AIN3 is with respect to HICOM.
+10
–10
78
78
GAIN
×
f
CLKIN
/64
f
CLKIN
/8
27
10
0 V/AV
DD
V max
V min
dB typ
dB typ
Normal Mode 50 Hz Rejection
Normal Mode 60 Hz Rejection
AIN3 Input Sampling Rate, f
S
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 20 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Gains of 1 to 4
For Gains of 8 to 128
Typically 30 k
±
10%; Typical Resistor Tempco is –30ppm/
°
C
AIN3 Input Impedance
2
AIN3 Sampling Capacitance
2
VBIAS Input Range
k
min
pF max
V min/max
Typically = REFIN(+) = 2.5 V
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
MCLK
All Inputs Except SCLK and MCLK IN
V
INL
, Input Low Voltage
±
1
±
10
μ
A max
μ
A max
Typically
±
20 nA
Typically
±
2
μ
A
0.8
0.4
2.0
V max
V max
V min
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V and 5 V
DV
DD
= 5 V Nominal
V
INH
, Input High Voltage
SCLK Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
SCLK Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
1.4/3
0.8/1.4
0.4/0.8
V min/V max
V min/V max
V min/V max
DV
DD
= 3 V Nominal
1/2.5
0.4/1.1
0.375/0.8
V min/V max
V min/V max
V min/V max
DV
DD
= 5 V Nominal
0.8
3.5
V max
V min
DV
DD
= 3 V Nominal
0.4
2.5
V max
V min
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
0.4
0.4
4
DV
DD
– 0.6
±
10
9
Binary
Offset Binary
V max
V max
V min
V min
μ
A max
pF typ
I
SINK
= 800
μ
A Except for MCLK OUT.
13
DV
DD
= 5 V
I
SINK
= 100
μ
A Except for MCLK OUT.
13
DV
DD
= 3 V
I
SOURCE
= 200
μ
A Except for MCLK OUT.
13
DV
DD
= 5 V
I
SOURCE
= 100
μ
A Except for MCLK OUT.
13
DV
DD
= 3 V
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
14
Data Output Coding
Unipolar Mode
Bipolar Mode
SYSTEM CALIBRATION
Low Level Input Channels (AIN1 and AIN2)
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
16
Input Span
16
(1.05
×
V
REF
)/GAIN
– (1.05
×
V
REF
)/GAIN V max
– (1.05
×
V
REF
)/GAIN V max
(0.8
×
V
REF
)/GAIN
(2.1
×
V
REF
)/GAIN
V max
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
V min
V max
High Level Input Channels (AIN3)
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
16
Input Span
16
(8.4
×
V
REF
)/GAIN
– (8.4
×
V
REF
)/GAIN
– (8.4
×
V
REF
)/GAIN
(6.4
×
V
REF
)/GAIN
(16.8
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
GAIN Is The Selected PGA Gain (1 to 128)
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
+2.7 to +3.3 or
+4.75 to +5.25
+2.7 to +5.25
V
V
For Specified Performance
For Specified Performance
DV
DD
Voltage
Power Supply Currents
AV
DD
Current
AV
= 3V or 5V. Gain = 1 to 4
Typically 0.22 mA. BUF = 0. f
CLK
IN
= 1 MHz
or 2.4576MHz
Typically 0.45 mA. BUF = 1. f
CLK
IN
= 1 MHz
or 2.4576 MHz
AV
= 3 V or 5V. Gain = 8 to 128
Typically 0.38mA. BUF = 0. f
CLK
IN
= 2.4576MHz
Typically 0.81mA. BUF = 1. f
CLK
IN
= 2.4576MHz
0.27
mA max
0.6
mA max
0.5
1.1
mA max
mA max
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