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參數(shù)資料
| 型號： | AD7707BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 3CH 20-TSSOP |
| 標準包裝： | 75 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極；2 個偽差分，單極；2 個偽差分，雙極 |
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AD7707
Rev. B | Page 20 of 52
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01
The setup register is an eight-bit register from which data can either be read or to which data can be written. Table 18 outlines the bit
designations for the setup register.
Table 18. Setup Register
MD1 (0)
MD0 (0)
G2 (0)
G1 (0)
G0 (0)
B/U (0)
BUF (0)
FSYNC (1)
Table 19.
Bit
Description
MD1, MD0
Operating mode selection bits.
G2 to G0
Gain selection bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 21.
B/U
Bipolar/unipolar operation. A 0 in this bit selects Bipolar operation. A 1 in this bit selects unipolar operation.
BUF
Buffer control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the
current flowing in the AVDD line is reduced. When this bit is high, the on-chip buffer is in series with the analog input
allowing the input to handle higher source impedances.
FSYNC
Filter synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, and the calibration
control logic are held in a reset state, and the analog modulator is held in its reset state. When this bit goes low, the
modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), that is, the settling
time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low.
Table 20. Operating Modes
MD1
MD0
Operating Mode
0
Normal mode: this is the normal mode of operation of the device whereby the device is performing normal conversions.
0
1
Self-calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the communications register.
This is a one-step calibration sequence and, when complete, the part returns to normal mode with MD1 and MD0
returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this self-
calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at
the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on
an internally-generated VREF/selected gain.
1
0
Zero-scale (ZS) system calibration: this activates zero-scale system calibration on the channel selected by CH1 and CH0
of the communications register. Calibration is performed at the selected gain on the input voltage provided at the
analog input during this calibration sequence. This input voltage should remain stable for the duration of the
calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part
returns to ormal
ode with MD1 and MD0 returning to 0, 0.
1
Full-scale (FS) system calibration: this activates full-scale system calibration on the selected input channel. Calibration is
performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This
input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when
calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in
the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0.
Table 21. Gain Selection
G2
G1
G0
Gain Setting
0
1
0
1
2
0
1
0
4
0
1
8
1
0
16
1
0
1
32
1
0
64
1
128
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