REF/GAIN TO 2.1 × V
參數(shù)資料
型號(hào)： AD7706BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CHAN 16TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個(gè)偽差分，單極; 3 個(gè)偽差分，雙極
配用： EVAL-AD7706EBZ-ND - BOARD EVALUATION FOR AD7706
AD7705/AD7706
Rev. C | Page 27 of 44
AD7705/AD7706
INPUT RANGE
(0.8
× V
REF/GAIN TO
2.1
× V
REF/GAIN)
UPPER LIMIT ON
AD7705 INPUT VOLTAGE
NOMINAL ZERO
SCALE POINT
OFFSET CALIBRATIONS MOVE
INPUT RANGE UP OR DOWN
LOWER LIMIT ON
AD7705/AD7706 INPUT VOLTAGE
–1.05
× V
REF/GAIN
–0V DIFFERENTIAL
GAIN CALIBRATIONS EXPAND
OR CONTRACT THE
AD7705/AD7706 INPUT RANGE
1.05
× V
REF/GAIN
01166-016
Figure 16. Span and Offset Limits
If the part is used in bipolar mode with a required span of
±0.4 × VREF/gain, the offset range that the system calibration can
handle is –0.65 × VREF/gain to +0.65 × VREF/gain. If
the part is used in bipolar mode with a required span of
±VREF/gain, the offset range that the system calibration can
handle is –0.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the
part is used in bipolar mode and required to remove an offset of
±0.2 × VREF/gain, the maximum span range that the system
calibration can handle is ±0.85 × VREF/gain.
Power-Up and Calibration
Upon power-up, the AD7705/AD7706 internally reset, setting
the contents of the internal registers to a known state. Default
values are loaded to all registers after a power-on or reset. The
default values contain nominal calibration coefficients for the
calibration registers. However, to ensure correct calibration for the
devices, a calibration routine should be performed after power-up.
The power dissipation and temperature drift of the AD7705/
AD7706 are low, and no warm-up time is required before the
initial calibration is performed. However, if an external reference
is used, it must be stabilized before calibration is initiated.
Similarly, if the clock source for the part is generated from a
crystal or resonator across the MCLK pins, the start-up time
for the oscillator circuit should elapse before a calibration is
initiated on the parts (see Figure 11).
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