參數(shù)資料
型號: AD7701ARSZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 7/20頁
文件大?。?/td> 0K
描述: IC ADC 16BIT LC2MOS MONO 28SSOP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 16
采樣率(每秒): 4k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 37mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
REV. E
AD7701
–15–
Synchronous External Clock Mode (SEC)
The SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry-standard
microprocessors such as the COPS series, 68HC11, and 68HC05.
The SEC mode also allows customized interfaces, using I/O
port pins, to microprocessors that do not have a direct fit with
the AD7701’s other modes.
As shown in Figure 20, a falling edge on
CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK.
After the LSB has been transmitted,
DRDY goes high and
SDATA goes three-state. If
CS is low and the AD7701 is still
transmitting data when a new data-word becomes available, the
old data-word continues to be transmitted and the new data is lost.
If
CS is taken high at any time during data transmission, SDATA
and SCLK will go three-state immediately. If
CS returns low,
the AD7701 will continue transmission with the same data bit.
If transmission has not been initiated and completed by the time
the next data-word becomes available, and if
CS is high, DRDY
will return high for four clock cycles, then fall as the new word
is loaded into the output register.
CLKIN (I)
DRDY (O)
SDATA (O)
DB15 (MSB)
DB14
DB2
DB1
DB0 (LSB)
HI-Z
SCLK (O)
HI-Z
CS (I)
72 CLKIN
CYCLES
Figure 19. SSC Mode Showing Data Timing Relative to SCLK
SCLK (I)
SDATA (O)
DB15
(MSB)
DB14
DB13
DB1
DB0
(LSB)
HI-Z
DRDY (O)
CS (I)
Figure 20. Timing Diagram for the SEC Mode
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