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參數(shù)資料
| 型號： | AD7699 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 8-Channel, 250 kSPS PulSAR㈢ ADC. |
| 中文描述： | 16位，8通道，250 kSPS的PulSAR系列㈢ADC的。 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 2041K |
| 代理商： | AD7699 |
AD7689
Preliminary Technical Data
Rev. PrC | Page 14 of 20
ground sense; CFG[12:10] = 10X
2
.
In this configuration, the IN+ is identified by the channel
in CFG[9:7]. Example: for IN0 = IN1+ and IN1 = IN1-,
CFG[9:7] = 000
2
; for IN1 = IN1+ and IN0 = IN1-,
CFG[9:7] = 001
2
Figure 14D, sows the inputs configured in any of the above
combinations as the AD7689 can be configured
dynamically.
Sequencer
The AD7689 includes a channel sequencer useful for scanning
channels in a IN0 to INn fashion. Channels are scanned as
single or pairs and with or without the temperature sensor, after
the last channel is sequenced.
The sequencer starts with IN0 and finishes with INn set in
CFG[9:7]. For paired channels, the channels are paired
depending on the last channel set in CFG[9:7]. Note that the
channel pairs are always paired IN(even) = INx+ and IN(odd) =
INx- regardless of CFG[7].
To enable the sequencer, CFG[2:1] are written to for initializing
the sequencer. After CFG[13:0] is updated, DIN must be held
low while reading data out (at least for bit 13) or the CFG will
begin updating again.
While operating in a sequence, the CFG can be changed by
writing 01
2
to CFG[2:1]. However, if changing CFG[11] (paired
or single channel) or CFG[9:7] (last channel in sequence), the
sequence will reinitialize and convert IN0 (or IN1) after CFG is
updated.
Examples
(only bits for input and sequencer are highlighted)
Scan all IN[7:0] referenced to COM = GND sense with
temperature sensor:
13
CFG
-
12
11
INCC
1
10
9
8
7
6
BW
-
5
4
3
2
SEQ
1
1
0
RB
-
INn
1
REF
-
1
0
1
1
-
-
0
Scan 3 paired channels without temperature sensor and
referenced to V
REF
/2:
13
CFG
-
12
11
INCC
0
10
9
8
7
6
BW
-
5
4
3
2
SEQ
1
1
0
RB
-
INn
0
REF
-
0
X
1
X
-
-
1
Scan 4 paired channels referenced to a GND sense with
temperature sensor:
13
CFG
-
Input Structure
Figure 15 shows an equivalent circuit of the input structure of
the AD7689.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN[7:0] and COM. Care must be taken to ensure
that the analog input signal does not exceed the supply rails by
12
11
INCC
0
10
9
8
7
6
BW
-
5
4
3
2
SEQ
1
1
0
RB
-
INn
1
REF
-
1
X
1
X
-
-
0
more than 0.3 V because this causes the diodes to become
forward biased and to start conducting current. These diodes
can handle a forward-biased current of 130 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s supplies are different from VDD. In such a case,
for example, an input buffer with a short circuit, the current
limitation can be used to protect the part.
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN-
OR COM
GND
VDD
-
Figure 15. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN
n
+ and COM or IN
n
+ and IN
n
-.
By using these differential inputs, signals common to both
inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs can be modeled as a parallel combination of the
capacitor, C
PIN
, and the network formed by the series
connection of R
IN
and C
IN
. C
PIN
is primarily the pin capacitance.
R
IN
is typically 3.5kΩ and is a lumped component made up of
serial resistors and the on resistance of the switches. C
IN
is
typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low Pass Filter
During the conversion phase, where the switches are opened,
the input impedance is limited to C
PIN
. While the AD7689 is
acquiring, R
IN
and C
IN
make a 1-pole, low-pass filter that reduces
undesirable aliasing effects and limits the noise from the driving
circuitry. The low pass filter can be programmed for the full
bandwidth or of the bandwidth with CFG[6] as shown in
Table 9.
DRIVER AMPLIFIER CHOICE
Although the AD7689 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7689. Note that the AD7689 has a
noise much lower than most of the other 16-bit ADCs and,
therefore, can be driven by a noisier amplifier to meet a given
system noise specification. The noise coming from the
amplifier is filtered by the AD7689 analog input circuit low-
pass filter made by R
IN
and C
IN
or by an external filter, if one
is used. Because the typical noise of the AD7689 is 35 μV rms
(with V
REF
= 5V), the SNR degradation due to the amplifier is
+
=
2
3dB
2
)
(
f
2
π
35
35
20log
N
LOSS
Ne
SNR
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