參數(shù)資料
型號: AD7693BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 500KSPS 10LFCSP
標準包裝: 5,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 21.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
配用: EVAL-AD7693CBZ-ND - BOARD EVALUATION FOR AD7693
AD7693
Rev. A | Page 14 of 24
ANALOG INPUTS
Figure 28 shows an equivalent circuit of the input structure of
the AD7693.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and to start conducting current. These diodes can handle
a forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, for
example, an input buffer with a short circuit, the current
limitation can be used to protect the part.
CIN
RIN
D1
D2
CPIN
IN+
OR IN–
GND
VDD
06
39
4-
02
7
Figure 28. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN. By using these
differential inputs, signals common to both inputs are rejected.
50
55
60
65
70
75
80
85
90
95
100
1
10
100
1000
10000
FREQUENCY (kHz)
CM
RR
(
d
B)
VREF = 5V
06
39
4-
02
8
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits the noise.
When the source impedance of the driving circuit is low, the
AD7693 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
–130
–125
–120
–115
–110
–105
–100
–95
–90
–85
–80
0
1020304050
6070
8090
33
50
100
0
63
94
-04
7
FREQUENCY (kHz)
T
HD
(
d
B)
250
VDD = 5V
Figure 30. THD vs. Analog Input Frequency and Source Resistance
DRIVER AMPLIFIER CHOICE
Although the AD7693 is easy to drive, the driver amplifier must
meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7693. The noise coming from
the driver is filtered by the AD7693 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7693 is 56 μV rms, the SNR degradation due to the
amplifier is
+
=
2
dB
3
2
dB
3
2
)
(
2
π
)
(
2
π
56
log
20
N
LOSS
Ne
f
Ne
f
SNR
where:
f3 dB is the input bandwidth in megahertz of the AD7693
(9 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
For ac applications, the driver should have a THD
performance commensurate with the AD7693.
For multichannel multiplexed applications, the driver
amplifier and the AD7693 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
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