參數(shù)資料
型號(hào)： AD768ACHIPS
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 30 MSPS D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 25 us SETTLING TIME, 16-BIT DAC, UUC31
封裝： 2.81 X 3.60 MM, DIE-31
文件頁(yè)數(shù)： 13/20頁(yè)
文件大小： 334K
代理商： AD768ACHIPS
AD768
REV. B
–13–
If properly implemented, ground planes can perform a host of
functions on high speed circuit boards: bypassing, shielding,
current transport, etc. In mixed signal design, the analog and
digital portions of the board should be distinct from each other,
with the analog ground plane confined to the areas covering
analog signal traces and the digital ground plane confined to
areas covering the digital interconnects.
All analog ground pins of the DAC, reference, and other analog
output components, should be tied directly to the analog ground
plane. T he two ground planes should be connected by a path
1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC
as shown in Figure 28. Care should be taken to ensure that the
ground plane is uninterrupted over crucial signal paths. On the
digital side, this includes the digital input lines running to the
DAC as well as any clock signals. On the analog side, this in-
cludes the DAC output signal, reference signal, and the supply
feeders.
T he use of wide runs or planes in the routing of power lines is
also recommended. T his serves the dual role of providing a low
series impedance power supply to the part, as well as, providing
some “free” capacitive decoupling to the appropriate ground
plane. Figure 29 illustrates the power plane layout used in the
AD768 evaluation board. T he AD768 evaluation board uses a
four layer P.C. board which illustrates good layout practices as
discussed above.
It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible, in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, some type of termination resistor should be considered.
T he necessity and value of this resistor will be dependent upon
the logic family used.
For maximum ac performance, the DAC should be mounted
directly to the circuit board; sockets should be avoided since
they introduce unwanted capacitive coupling between adjacent
pins of the device.
POWE R SUPPLY AND DE COUPLING
One of the most important external components associated with
high speed designs are the capacitors used to bypass the power
supplies. Both selection and placement of these capacitors can
be critical and, to a large extent, dependent upon the specifics of
the system configuration. T he dominant consideration in the
selection of bypass capacitors for the AD768 is the minimization
of the series resistance and inductance. Many capacitors will
begin to look inductive at 20 MHz and above. Ceramic and film
type capacitors generally feature lower series inductance than
tantalum or electrolytic types.
It is recommended that each power supply to the AD768 be de-
coupled by a 0.1
μ
F capacitor located as close to the device pins
as possible. Surface-mount chip capacitors, by virtue of their
low parasitic inductance, are preferable to through-hole types.
Some series inductance between the DAC supply pins and the
power supply plane may help to provide additional filtering of
high frequency power supply noise. T his inductance can be gen-
erated by using small ferrite beads.
A clean digital supply may be generated using the circuit shown
in Figure 30. T he circuit consists of a differential LC filter with
separate power supply and return lines. Lower noise can be at-
tained using low ESR (Equivalent Series Resistance) type elec-
trolytic and tantalum capacitors.
FERRITE
BEADS
100μF
ELECT.
10–20μF
TANT.
0.1μF
CER.
V
DD
DCOM
+5V
DGND
+5V
POWER SUPPLY
TTL/CMOS
LOGIC
CIRCUITS
Figure 30. Differential LC Filter for Single +5 V
Applications
APPLICAT IONS
USING T HE AD768 AS A MULT IPLY ING DAC
T he AD768 can be easily configured as a multiplying DAC
since I
REFIN
can be modulated from 1 mA to 7 mA. T he refer-
ence amplifier sets the maximum multiplying bandwidth to 15
MHz, while any external capacitor to the NR node serves to
limit the bandwidth according to Figure 7. I
REFIN
can be easily
modulated by properly scaling and summing into the IREFIN
node the modulating signal. Figure 31 demonstrates how the
modulating signal VMOD can be properly scaled and converted
to a current via R
REFMOD
such that its peak current does not ex-
ceed 3.0 mA. Figure 32 shows the AD768’s typical distortion
versus the reference channel frequency.
6
3
AD768
R
REF
625
IREFIN
REFOUT
1μF
R
REFMOD
VMOD
VMOD
R
REFMOD
≤
±
3.0mA
Figure 31. Typical Multiplying DAC Application
FREQUENCY – kHz
T
–75
–40
250
2500
500
750
1000
1250
1500
1750
2000
2250
–70
–60
–55
–50
–45
–65
I
REF
= 4.0+/–3 mA
I
REF
= 4.0+/–2 mA
I
REF
= 5.0+/–1 mA
Figure 32. Reference Channel Distortion vs. Frequency
相關(guān)PDF資料
PDF描述
AD768-EB 16-Bit, 30 MSPS D/A Converter
AD768AR 16-Bit, 30 MSPS D/A Converter
AD768 16-Bit, 30 MSPS D/A Converter(16位,30MSPS D/A轉(zhuǎn)換器)
AD7690 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
AD7693 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD768AF/QMLR 制造商:Analog Devices 功能描述:
AD768AR 功能描述:IC DAC 16BIT 30MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD768AR-REEL 制造商:Analog Devices 功能描述:DAC 1-CH R-2R/Current Steering 16-bit 28-Pin SOIC W T/R
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