參數(shù)資料
型號(hào)： AD7689ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 250KSPS 8CH 20LFCSP
產(chǎn)品培訓(xùn)模塊： Power Line Monitoring
Motor Control
產(chǎn)品變化通告： Startup Circuitry Design Improvement Change 15/April/2009
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-VQ
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，雙極；4 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
AD7682/AD7689
Data Sheet
Rev. D | Page 28 of 32
CHANNEL SEQUENCER
The AD7682/AD7689 include a channel sequencer useful for
scanning channels in a repeated fashion. Channels are scanned
as singles or pairs, with or without the temperature sensor, after
the last channel is sequenced.
The sequencer starts with IN0 and finishes with IN[7:0] set in
CFG[9:7]. For paired channels, the channels are paired depend-
ing on the last channel set in CFG[9:7]. Note that in sequencer
mode, the channels are always paired with the positive input on
the even channels (IN0, IN2, IN4, IN6), and with the negative
input on the odd channels (IN1, IN3, IN5, IN7). For example,
setting CFG[9:7] = 110 or 111 scans all pairs with the positive
inputs dedicated to IN0, IN2, IN4, and IN6.
CFG[2:1] are used to enable the sequencer. After the CFG
register is updated, DIN must be held low while reading data
out for Bit 13, or the CFG register begins updating again.
Note that while operating in a sequence, some bits of the CFG
register can be changed. However, if changing CFG[11] (paired
or single channel) or CFG[9:7] (last channel in sequence), the
sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after
the CFG register is updated.
Figure 39 details the timing for all three modes without a busy
indicator. Refer to the Read/Write Spanning Conversion
Conversion Without a Busy Indicator section for more details.
The sequencer can also be used with the busy indicator and
details for these timings can be found in the General Timing
For sequencer operation, the CFG register should be set during
the (n 1) phase after power-up. On phase (n), the sequencer
setting takes place and acquires IN0. The first valid conversion
result is available at phase (n + 1). After the last channel set in
CFG[9:7] is converted, the internal temperature sensor data is
output (if enabled), followed by acquisition of IN0.
Examples
With all channels configured for unipolar mode to GND,
including the internal temperature sensor, the sequence scans in
the following order:
IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, …
For paired channels with the internal temperature sensor
enabled, the sequencer scans in the following order:
IN0, IN2, IN4, IN6, TEMP, IN0, …
Note that IN1, IN3, IN5, and IN7 are referenced to a GND
sense or VREF/2, as detailed in the Input Configurations section.
ACQUISITION
(n – 1) UNDEFINED
ACQUISITION
(n), IN0
ACQUISITION
(n + 1), IN1
ACQUISITION
(n + 2), IN2
PHASE
POWER
UP
EOC
SOC
EOC
CONVERSION
(n – 1) UNDEFINED
CONVERSION
(n), IN0
CONVERSION
(n + 1), IN1
CONVERSION
(n – 2) UNDEFINED
07
35
3-
0
4
6
tCONV
tCYC
tDATA
CNV
DIN
SDO
XXX
MSB
XXX
MSB
XXX
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
DATA IN0
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 3)
XXX
MSB
IN0
MSB
IN1
DIN
SDO
DATA IN1
DATA IN0
DATA IN1
DIN
CFG (n)
SDO
SCK
1
NOTE 1
16
NOTE 2
2
1
SCK
116
16
nn
n
n + 1
n
1
SCK
1
116
16
1
CFG (n)
RDC
RAC
RSC
CFG (n)
Figure 39. General Channel Sequencer Timing Without a Busy Indicator
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