參數(shù)資料
型號: AD7688BRMZRL7
廠商: Analog Devices Inc
文件頁數(shù): 26/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 500KSPS 10MSOP
標準包裝: 1,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 21.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
AD7688
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02973-
005
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7688
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead MSOP Pin Configuration
02
973-
006
1
REF
2
VDD
3
IN+
4
IN–
5
GND
10 VIO
9SDI
8SCK
7SDO
6 CNV
NOTES
1. FOR THE LFCSP PACKAGE ONLY,
THE EXPOSED PADDLE MUST BE
CONNECTED TO GND.
TOP VIEW
(Not to Scale)
AD7688
Figure 6. 10-Lead
QFN (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Function
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain or CS. In CS mode, it enables the SDO pin when low. In chain mode, the
data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EPAD
N/A
For the LFCSP package only, the exposed paddle must be connected to GND.
1AI = Analog Input, DI = Digital Input, DO = Digital Output, P = Power, and N/A = not applicable.
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