參數(shù)資料
型號: AD7684BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 100 kSPS PulSAR Differential ADC in MSOP
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187-AA, MSOP-8
文件頁數(shù): 12/16頁
文件大?。?/td> 452K
代理商: AD7684BRM
AD7684
APPLICATION INFORMATION
Rev. 0 | Page 12 of 16
SW+
MSB
16,384C
+IN
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
–IN
4C
2C
C
C
32,768C
SW–
MSB
16,384C
LSB
4C
2C
C
C
32,768C
0
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7684 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of convert-
ing 100,000 samples per second (100 kSPS) and powers down
between conversions. When operating at 10 kSPS, for example,
it consumes typically 150 μW with a 2.7 V supply, ideal for
battery-powered applications.
The AD7684 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7684 is specified from 2.7 V to 5.5 V. It is housed in a
8-lead MSOP package.
CONVERTER OPERATION
The AD7684 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and IN inputs. When the
acquisition phase is complete and the CS input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs, +IN and IN, captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between GND and REF, the comparator
input varies by binary-weighted voltage steps (V
REF
/2,
V
REF
/4...V
REF
/65536). The control logic toggles these switches,
starting with the MSB, in order to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7684 is shown in
Figure 21 and Table 8.
100...000
100...001
100...010
011...101
011...110
011...111
A
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
0
Figure 21. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Analog Input
V
REF
= 5 V
FSR – 1 LSB
4.999847 V
Midscale + 1 LSB
152.6 μV
Midscale
0 V
Midscale – 1 LSB
–152.6 μV
–FSR + 1 LSB
–4.999847 V
–FSR
–5 V
Description
Digital Output Code Hexa
7FFF
1
0001
0000
FFFF
8001
8000
2
1
This is also the code for an overranged analog input (V
+IN
– V
–IN
above
V
REF
– V
GND
).
2
This is also the code for an underranged analog input (V
+IN
– V
–IN
below V
REF
+ V
GND
).
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