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參數(shù)資料
| 型號： | AD7680ARMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SRL 100KSPS 8MSOP |
| 標準包裝： | 50 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7680
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS1
Table 4. VDD = 2.5 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter
3 V
5 V
Unit
Description
250
kHz min
2.5
MHz max
tCONVERT
20 × tSCLK
min
tQUIET
100
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS to SCLK setup time
48
35
ns max
Delay from CS until SDATA three-state disabled
t43
120
80
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to data valid hold time
45
35
ns max
SCLK falling edge to SDATA high impedance
1
μs typ
Power up time from full power-down
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power vs. Throughput Rate section.
03643-0-002
200
μAI
OL
200
μAI
OH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7680ARMZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7680 MSOP8 |
| AD7680BR | 制造商:Analog Devices 功能描述:- Tape and Reel |
| AD7680BRJ | 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT SERL 6PIN SOT-23 - Bulk |
| AD7680BRJ-R2 | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Serial 6-Pin SOT-23 T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT SERL 6PIN SOT-23 - Tape and Reel |
| AD7680BRJ-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Serial 6-Pin SOT-23 T/R |
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