參數(shù)資料
型號: AD7679ASTRL
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
中文描述: 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: LOW PROFILE, MS-026BBC, LQFP-48
文件頁數(shù): 7/28頁
文件大小: 1186K
代理商: AD7679ASTRL
AD7679
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7679 Absolute Maximum Ratings
1
Parameter
Analog Inputs
IN+
2
, IN–
2
, REF, REFBUFIN, REFGND
to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
Digital Inputs
Internal Power Dissipation
3
Internal Power Dissipation
4
Junction Temperature
Storage Temperature Range
Lead Temperature Range
(Soldering 10 sec)
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2
See An
section.
alog Inputs
3
Specification is for device in free air: 48-Lead LQFP: θ
JA
= 91°C/W,
θ
JC
= 30°C/W.
4
Specification is for device in free air: 48-Lead LFCSP: θ
JA
= 26°C/W.
Rating
AVDD + 0.3 V to
AGND – 0.3 V
±0.3 V
–0.3 V to +7 V
±7 V
–0.3 V to +7 V
–0.3 V to DVDD + 0.3 V
700 mW
2.5 W
150°C
–65°C to +150°C
300°C
TO OUTPUT
PIN
C
L
60pF
1
500
μ
A
I
OH
1.6mA
I
OL
1.4V
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
1
03085–0–002
Figure 2. Load Circuit for Digital Interface Timing
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
03085–0–003
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 7 of 28
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