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| 型號： | AD7675ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 399K |
| 代理商： | AD7675ASTRL |
REV. 0
–3–
AD7675
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read
After Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
t
1
t
2
t
3
t
4
5
10
ns
μ
s
ns
μ
s
30
1.25
t
5
t
6
t
7
t
8
t
9
2
ns
ns
μ
s
μ
s
ns
10
1.25
8.75
10
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t
10
t
11
t
12
t
13
1.25
μ
s
ns
ns
ns
45
40
15
5
Refer to Figures 16 and 17 (Master Serial Interface Modes)
1
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
2
Internal SCLK Period
2
Internal SCLK HIGH
2
Internal SCLK LOW
2
SDOUT Valid Setup Time
2
SDOUT Valid Hold Time
2
SCLK Last Edge to SYNC Delay
2
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert
2
CNVST
LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
ns
525
3
25
12
7
4
2
3
40
10
10
10
See Table I
1.25
25
Refer to Figures 18 and 19 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
(–40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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