TIMING SPECIFICATIONS (continued) Parameter Symbol Min Typ Max Unit Refer to Figures 13, 14," />
參數(shù)資料
型號： AD7671ACPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 19/24頁
文件大?。?/td> 0K
描述： IC ADC 16BIT CMOS 1MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 125mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極
配用： EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671
AD7671
–4–
TIMING SPECIFICATIONS (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
ms
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Read during Convert)
t17
25/275/525
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
t18
4ns
Internal SCLK Period
3
t19
25
40
ns
Internal SCLK HIGH
3
t20
15
ns
Internal SCLK LOW
3
t21
9.5
ns
SDOUT Valid Setup Time
3
t22
4.5
ns
SDOUT Valid Hold Time
3
t23
2ns
SCLK Last Edge to SYNC Delay
3
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert
3
t28
See Table II
ms
CNVST LOW to SYNC Asserted Delay
t29
0.75/1/1.25
ms
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5ns
External SCLK Active Edge to SDOUT Delay
t32
316
ns
SDIN Setup Time
t33
5ns
SDIN Hold Time
t34
5ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
0011
DIVSCLK[0]
0101
Unit
SYNC to SCLK First Edge Delay Minimum
t18
420
2020
ns
Internal SCLK Period Minimum
t19
25
50
100
200
ns
Internal SCLK Period Maximum
t19
40
70
140
280
ns
Internal SCLK HIGH Minimum
t20
15
25
50
100
ns
Internal SCLK LOW Minimum
t21
924
4999
ns
SDOUT Valid Setup Time Minimum
t22
4.5
22
ns
SDOUT Valid Hold Time Minimum
t23
2430
89
ns
SCLK Last Edge to SYNC Delay Minimum
t24
360
140
300
ns
BUSY HIGH Width Maximum (Warp)
t28
1.5
2
3
5.25
ms
BUSY HIGH Width Maximum (Normal)
t28
1.75
2.25
3.25
5.5
ms
BUSY HIGH Width Maximum (Impulse)
t28
2
2.5
3.5
5.75
ms
Specifications subject to change without notice.
REV. C
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