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參數(shù)資料
| 型號(hào)： | AD7665ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/23頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT CMOS 5V 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 570k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 74mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類(lèi)型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
| 配用： | EVAL-AD7665CBZ-ND - BOARD EVALUATION FOR AD7665 |
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REV.
AD7665
–21–
be seeing a discontinuous clock, an initial word reading has to be
done after the ADSP-21065L has been reset to ensure that the
Serial Port is properly synchronized to this clock during each
following data read operation.
RFS
ADSP-21065L*
SHARC
CNVST
AD7665*
CS
SYNC
RD
DR
RCLK
FLAG OR TFS
SDOUT
SCLK
INVSYNC
INVSCLK
EXT/
INT
RDC/SDIN
SER/
PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the ADSP-21065L Using the
Serial Master Mode
APPLICATION HINTS
Layout
The AD7665 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The printed circuit board that houses the AD7665 should be
designed so the analog and digital sections are separated and con-
fined to certain areas of the board. This facilitates the use of ground
planes that can be easily separated. Digital and analog ground
planes should be joined in only one place, preferably underneath
the AD7665, or at least as close as possible to the AD7665. If the
AD7665 is in a system where multiple devices require analog-to-
digital ground connections, the connection should still be made
at one point only, a star ground point that should be established
as close as possible to the AD7665.
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7665 to avoid noise
coupling. Fast switching signals like
CNVST or clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.
The power supply lines to the AD7665 should use as large a trace
as possible to provide low impedance paths and reduce the effect
of glitches on the power supply lines. Good decoupling is also
important to lower the supplies impedance presented to the
AD7665 and to reduce the magnitude of the supply spikes. Decou-
pling ceramic capacitors, typically 100 nF, should be placed on all
of the power supply pins AVDD, DVDD, and OVDD close to and
ideally right up against these pins and their corresponding ground
pins. Additionally, low ESR 10 F capacitors should be located
in the vicinity of the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7665 can be either a separate supply
or come from the analog supply, AVDD, or from the digital inter-
face supply, OVDD. When the system digital supply is noisy, or
fast switching digital signals are present, it is recommended, if
no separate supply is available, to connect the DVDD digital
supply to the analog supply AVDD through an RC filter as shown
in Figure 5 and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. When
DVDD is powered from the system supply, it is useful to insert
a bead to further reduce high frequency spikes.
The AD7665 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and should
be a low impedance return to the reference because it carries
pulsed currents. AGND is the ground to which most internal ADC
analog signals are referenced. This ground must be connected
with the least resistance to the analog ground plane. DGND must
be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.
The layout of the decoupling of the reference voltage is important.
The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
Evaluating the AD7665 Performance
A recommended layout for the AD7665 is outlined in the evalua-
tion board for the AD7665. The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the Eval-
Control Board.
C
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| AD7665ACPZRL | 功能描述:IC ADC 16BIT CMOS 5V 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
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